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Searched refs:MCTL_MR2 (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a33.h175 #define MCTL_MR2 0x18 /* CWL=8 */ macro
Ddram_sun8i_a83t.h197 #define MCTL_MR2 0x18 /* CWL=8 */ macro
Ddram_sun6i.h349 #define MCTL_MR2 ((MCTL_TCWL - 5) << 3) macro
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun8i_a33.c135 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
Ddram_sun8i_a83t.c136 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
Ddram_sun6i.c124 writel(MCTL_MR2, &mctl_phy->mr2); in mctl_channel_init()