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Searched refs:MESA_FORMAT_B4G4R4A4_UNORM (Results 1 – 25 of 31) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_tex.h72 [ MESA_FORMAT_B4G4R4A4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
102 [ MESA_FORMAT_B4G4R4A4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 },
Dr200_blit.c50 case MESA_FORMAT_B4G4R4A4_UNORM: in r200_check_blit()
153 case MESA_FORMAT_B4G4R4A4_UNORM: in emit_tx_setup()
337 case MESA_FORMAT_B4G4R4A4_UNORM: in emit_cb_setup()
Dradeon_pixel_read.c71 return MESA_FORMAT_B4G4R4A4_UNORM; in gl_format_and_type_to_mesa_format()
Dradeon_texture.c610 _radeon_texformat_argb4444 = MESA_FORMAT_B4G4R4A4_UNORM; in radeonInitTextureFormats()
/external/mesa3d/src/mesa/drivers/dri/nouveau/
Dnv04_surface.c48 case MESA_FORMAT_B4G4R4A4_UNORM: in swzsurf_format()
87 case MESA_FORMAT_B4G4R4A4_UNORM: in surf2d_format()
126 case MESA_FORMAT_B4G4R4A4_UNORM: in rect_format()
165 case MESA_FORMAT_B4G4R4A4_UNORM: in sifm_format()
Dnv20_state_tex.c96 case MESA_FORMAT_B4G4R4A4_UNORM: in get_tex_format_pot()
137 case MESA_FORMAT_B4G4R4A4_UNORM: in get_tex_format_rect()
Dnv04_state_tex.c47 case MESA_FORMAT_B4G4R4A4_UNORM: in get_tex_format()
Dnv10_state_tex.c102 case MESA_FORMAT_B4G4R4A4_UNORM: in get_tex_format_pot()
/external/mesa3d/src/mesa/main/
Dtexformat.c74 RETURN_IF_SUPPORTED(MESA_FORMAT_B4G4R4A4_UNORM); in _mesa_choose_tex_format()
95 RETURN_IF_SUPPORTED(MESA_FORMAT_B4G4R4A4_UNORM); in _mesa_choose_tex_format()
98 RETURN_IF_SUPPORTED(MESA_FORMAT_B4G4R4A4_UNORM); in _mesa_choose_tex_format()
Dformats.h348 MESA_FORMAT_B4G4R4A4_UNORM, /* AAAA RRRR GGGG BBBB */ enumerator
Dformats.c858 case MESA_FORMAT_B4G4R4A4_UNORM: in _mesa_uncompressed_format_to_type_and_comps()
1524 case MESA_FORMAT_B4G4R4A4_UNORM: in _mesa_format_matches_format_and_type()
Dformats.csv67 MESA_FORMAT_B4G4R4A4_UNORM , packed, 1, 1, 1, un4 , un4 , un4 , un4 , zyxw, rgb
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_tex.h71 [ MESA_FORMAT_B4G4R4A4_UNORM ] = { RADEON_TXFORMAT_ARGB4444 | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 },
Dradeon_blit.c50 case MESA_FORMAT_B4G4R4A4_UNORM: in r100_check_blit()
186 case MESA_FORMAT_B4G4R4A4_UNORM: in emit_cb_setup()
Dradeon_pixel_read.c71 return MESA_FORMAT_B4G4R4A4_UNORM; in gl_format_and_type_to_mesa_format()
Dradeon_texture.c610 _radeon_texformat_argb4444 = MESA_FORMAT_B4G4R4A4_UNORM; in radeonInitTextureFormats()
/external/mesa3d/prebuilt-intermediates/main/
Dformat_fallback.c303 return MESA_FORMAT_B4G4R4A4_UNORM; in _mesa_format_fallback_rgbx_to_rgba()
/external/mesa3d/src/mesa/drivers/dri/i915/
Di915_context.c114 ctx->TextureFormatSupported[MESA_FORMAT_B4G4R4A4_UNORM] = true; in intel_init_texture_formats()
Di830_texstate.c56 case MESA_FORMAT_B4G4R4A4_UNORM: in translate_texture_format()
Di915_texstate.c57 case MESA_FORMAT_B4G4R4A4_UNORM: in translate_texture_format()
Dintel_blit.c462 case MESA_FORMAT_B4G4R4A4_UNORM: in intelClearWithBlit()
Di915_vtbl.c550 [MESA_FORMAT_B4G4R4A4_UNORM] = DV_PF_4444 | DITHER_FULL_ALWAYS,
Di830_vtbl.c590 [MESA_FORMAT_B4G4R4A4_UNORM] = DV_PF_4444,
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_surface_formats.c48 [MESA_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM, in brw_isl_format_for_mesa_format()
/external/mesa3d/src/mesa/state_tracker/
Dst_format.c85 case MESA_FORMAT_B4G4R4A4_UNORM: in st_mesa_format_to_pipe_format()
569 return MESA_FORMAT_B4G4R4A4_UNORM; in st_pipe_format_to_mesa_format()

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