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Searched refs:MPLL_CON0_VAL (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dclock_init_exynos4.c87 writel(MPLL_CON0_VAL, &clk->mpll_con0); in system_clock_init()
Dexynos4_setup.h360 #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) macro
/external/u-boot/board/samsung/trats/
Dtrats.c342 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); in board_clock_init()
Dsetup.h249 #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) macro