Searched refs:MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET (Results 1 – 17 of 17) sorted by relevance
168 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
455 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in enable_lvds()543 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in enable_spi_display()
408 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) in setup_display_clock()
471 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display_b850v3()517 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display_bx50v3()
351 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
482 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
416 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
408 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); in setup_display()
339 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
519 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
537 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
597 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
781 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
651 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET | in setup_display()
500 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 macro
719 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()
457 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); in setup_display()