Searched refs:MaskedOp (Results 1 – 4 of 4) sorted by relevance
317 bool isMaskRequired(const Instruction *I) { return (MaskedOp.count(I) != 0); } in isMaskRequired()477 SmallPtrSet<const Instruction *, 8> MaskedOp; variable
817 MaskedOp.insert(LI); in blockCanBePredicated()831 MaskedOp.insert(SI); in blockCanBePredicated()
1475 bool isMaskRequired(const Instruction *I) { return (MaskedOp.count(I) != 0); } in isMaskRequired()1590 SmallPtrSet<const Instruction *, 8> MaskedOp; member in __anon63bf7e8f0111::LoopVectorizationLegality4879 MaskedOp.insert(LI); in blockCanBePredicated()4901 MaskedOp.insert(SI); in blockCanBePredicated()
35708 static bool getParamsForOneTrueMaskedElt(MaskedLoadStoreSDNode *MaskedOp, in getParamsForOneTrueMaskedElt() argument35711 int TrueMaskElt = getOneTrueElt(MaskedOp->getMask()); in getParamsForOneTrueMaskedElt()35717 EVT EltVT = MaskedOp->getMemoryVT().getVectorElementType(); in getParamsForOneTrueMaskedElt()35718 Addr = MaskedOp->getBasePtr(); in getParamsForOneTrueMaskedElt()35721 Addr = DAG.getMemBasePlusOffset(Addr, Offset, SDLoc(MaskedOp)); in getParamsForOneTrueMaskedElt()35724 Index = DAG.getIntPtrConstant(TrueMaskElt, SDLoc(MaskedOp)); in getParamsForOneTrueMaskedElt()35725 Alignment = MinAlign(MaskedOp->getAlignment(), EltVT.getStoreSize()); in getParamsForOneTrueMaskedElt()