Searched refs:MemRegs (Results 1 – 3 of 3) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1458 SmallSet<unsigned, 4> &MemRegs, in IsSafeAndProfitableToMove() argument
1489 if (Reg != Base && !MemRegs.count(Reg)) in IsSafeAndProfitableToMove()
1495 if (MemRegs.size() <= 4) in IsSafeAndProfitableToMove()
1498 return AddedRegPressure.size() <= MemRegs.size() * 2; in IsSafeAndProfitableToMove()
1639 SmallSet<unsigned, 4> MemRegs; in RescheduleOps() local
1642 MemRegs.insert(Ops[i]->getOperand(0).getReg()); in RescheduleOps()
1650 MemOps, MemRegs, TRI); in RescheduleOps()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2060 SmallSet<unsigned, 4> &MemRegs, in IsSafeAndProfitableToMove() argument
2081 if (Reg != Base && !MemRegs.count(Reg)) in IsSafeAndProfitableToMove()
2087 if (MemRegs.size() <= 4) in IsSafeAndProfitableToMove()
2090 return AddedRegPressure.size() <= MemRegs.size() * 2; in IsSafeAndProfitableToMove()
2237 SmallSet<unsigned, 4> MemRegs; in RescheduleOps() local
2240 MemRegs.insert(Ops[i]->getOperand(0).getReg()); in RescheduleOps()
2248 MemOps, MemRegs, TRI, AA); in RescheduleOps()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2012 SmallSet<unsigned, 4> &MemRegs, in IsSafeAndProfitableToMove() argument
2042 if (Reg != Base && !MemRegs.count(Reg)) in IsSafeAndProfitableToMove()
2048 if (MemRegs.size() <= 4) in IsSafeAndProfitableToMove()
2051 return AddedRegPressure.size() <= MemRegs.size() * 2; in IsSafeAndProfitableToMove()
2191 SmallSet<unsigned, 4> MemRegs; in RescheduleOps() local
2194 MemRegs.insert(Ops[i]->getOperand(0).getReg()); in RescheduleOps()
2202 MemOps, MemRegs, TRI); in RescheduleOps()
|