Home
last modified time | relevance | path

Searched refs:NVBL_PLLP_KHZ (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/
Dcpu.h13 #define NVBL_PLLP_KHZ 216000 macro
17 #define NVBL_PLLP_KHZ 408000 macro
Dcpu.c392 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); in clock_enable_coresight()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dcpu.c166 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in tegra124_init_clocks()
/external/u-boot/arch/arm/mach-tegra/tegra114/
Dcpu.c158 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); in t114_init_clocks()