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Searched refs:NumArgRegs (Results 1 – 7 of 7) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeISelLowering.cpp664 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_MBlaze_AssignReg() local
665 unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs); in CC_MBlaze_AssignReg()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp1215 unsigned NumArgRegs = 77; in LowerFormalArguments() local
1221 for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) { in LowerFormalArguments()
1279 const unsigned NumArgRegs = ArgLocs.size(); in LowerCall() local
1324 if (ArgRegIdx != NumArgRegs) { in LowerCall()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp1537 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC_SVR4_Custom_AlignArgRegs() local
1539 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignArgRegs()
1545 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC_SVR4_Custom_AlignArgRegs()
1565 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC_SVR4_Custom_AlignFPArgRegs() local
1567 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignFPArgRegs()
1571 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC_SVR4_Custom_AlignFPArgRegs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp138 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_SkipOdd() local
142 if (RegNum != NumArgRegs && RegNum % 2 == 1) in CC_SkipOdd()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp3135 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
3143 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
3163 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
3166 int RegsLeft = NumArgRegs - RegNum; in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
3170 if (RegNum != NumArgRegs && RegsLeft < 4) { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
3189 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
3195 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2677 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
2685 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
2705 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
2711 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1445 unsigned NumArgRegs) { in allocateSGPR32InputImpl() argument