| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Vectorize/ |
| D | VPlanHCFGBuilder.cpp | 273 unsigned NumSuccs = TI->getNumSuccessors(); in buildPlainCFG() local
275 if (NumSuccs == 1) { in buildPlainCFG()
279 } else if (NumSuccs == 2) { in buildPlainCFG()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | ScheduleDAG.cpp | 101 assert(N->NumSuccs < UINT_MAX && "NumSuccs will overflow!"); in addPred()
103 ++N->NumSuccs; in addPred()
148 assert(N->NumSuccs > 0 && "NumSuccs will underflow!"); in removePred()
150 --N->NumSuccs; in removePred()
358 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) { in VerifySchedule()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAG.cpp | 99 assert(N->NumSuccs < UINT_MAX && "NumSuccs will overflow!"); in addPred()
101 ++N->NumSuccs; in addPred()
150 assert(N->NumSuccs > 0 && "NumSuccs will underflow!"); in removePred()
152 --N->NumSuccs; in removePred()
387 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) { in VerifyScheduledDAG()
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| D | ScheduleDAGPrinter.cpp | 42 return (Node->NumPreds > 10 || Node->NumSuccs > 10); in isNodeHidden()
|
| D | ScheduleDAGInstrs.cpp | 995 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) { in buildSchedGraph()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | ScheduleDAG.cpp | 140 assert(N->NumSuccs < std::numeric_limits<unsigned>::max() && in addPred()
143 ++N->NumSuccs; in addPred()
190 assert(N->NumSuccs > 0 && "NumSuccs will underflow!"); in removePred()
192 --N->NumSuccs; in removePred()
403 if (SUnit.NumPreds == 0 && SUnit.NumSuccs == 0) { in VerifyScheduledDAG()
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| D | ScheduleDAGPrinter.cpp | 40 return (Node->NumPreds > 10 || Node->NumSuccs > 10); in isNodeHidden()
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| D | ScheduleDAGInstrs.cpp | 835 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) { in buildSchedGraph()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 158 unsigned NumSuccs = MBB->succ_size(); in runOnMachineFunction() local
187 if ((NumSuccs == 2) && LayoutSucc && (LayoutSucc->pred_size() == 1)) { in runOnMachineFunction()
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| D | HexagonSubtarget.cpp | 347 if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) { in adjustSchedDependency()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 147 unsigned NumSuccs = MBB->succ_size(); in runOnMachineFunction() local
176 if ((NumSuccs == 2) && LayoutSucc && (LayoutSucc->pred_size() == 1)) { in runOnMachineFunction()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 248 unsigned NumSuccs; // # of SDep::Data sucss.
281 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
295 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
308 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 269 unsigned NumSuccs; // # of SDep::Data sucss.
310 NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
326 NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
341 NodeNum(BoundaryID), NodeQueueId(0), NumPreds(0), NumSuccs(0),
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1791 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
1798 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
1860 if (!N->isMachineOpcode() || !SU->NumSuccs) in MayReduceRegPressure()
1907 if (!N || !N->isMachineOpcode() || !SU->NumSuccs) in RegPressureDiff()
2056 if (SU->NumSuccs && N->isMachineOpcode()) { in UnscheduledNode()
2507 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in canEnableCoalescing()
2729 if (SU->NumSuccs != 0) in PrescheduleNodesWithMultipleUses()
2757 if (PredSU->NumSuccs == 1) in PrescheduleNodesWithMultipleUses()
2774 if (PredSuccSU->NumSuccs == 0) in PrescheduleNodesWithMultipleUses()
2925 if (left->NumSuccs == 0 && right->NumSuccs != 0) in operator ()()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | GCNILPSched.cpp | 89 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
97 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1900 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
1907 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
1970 if (!N->isMachineOpcode() || !SU->NumSuccs) in MayReduceRegPressure()
2016 if (!N || !N->isMachineOpcode() || !SU->NumSuccs) in RegPressureDiff()
2163 if (SU->NumSuccs && N->isMachineOpcode()) { in unscheduledNode()
2582 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in canEnableCoalescing()
2803 if (SU.NumSuccs != 0) in PrescheduleNodesWithMultipleUses()
2830 if (PredSU->NumSuccs == 1) in PrescheduleNodesWithMultipleUses()
2846 if (PredSuccSU->NumSuccs == 0) in PrescheduleNodesWithMultipleUses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 2026 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
2033 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
2094 if (!N->isMachineOpcode() || !SU->NumSuccs) in MayReduceRegPressure()
2140 if (!N || !N->isMachineOpcode() || !SU->NumSuccs) in RegPressureDiff()
2288 if (SU->NumSuccs && N->isMachineOpcode()) { in unscheduledNode()
2707 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in canEnableCoalescing()
2929 if (SU.NumSuccs != 0) in PrescheduleNodesWithMultipleUses()
2956 if (PredSU->NumSuccs == 1) in PrescheduleNodesWithMultipleUses()
2972 if (PredSuccSU->NumSuccs == 0) in PrescheduleNodesWithMultipleUses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 272 unsigned NumSuccs = 0; ///< # of SDep::Data sucss.
|