| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rv1108.c | 31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
33 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
34 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
80 freq = OSC_HZ; in rkclk_pll_get_rate()
140 return DIV_TO_RATE(OSC_HZ, div); in rv1108_saradc_get_clk()
147 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
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| D | clk_rk3036.c | 33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
51 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
193 return OSC_HZ; in rkclk_pll_get_rate()
234 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; in rockchip_mmc_get_clk()
250 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
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| D | clk_rk3368.c | 35 #define OSC_HZ (24 * 1000 * 1000) macro
44 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
45 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
72 return OSC_HZ; in rkclk_pll_get_rate()
93 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
182 pll_rate = OSC_HZ; in rk3368_mmc_get_clk()
435 return DIV_TO_RATE(OSC_HZ, div); in rk3368_saradc_get_clk()
442 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3368_saradc_set_clk()
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| D | clk_rk3128.c | 31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
78 u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0; in pll_para_config()
262 return OSC_HZ; in rkclk_pll_get_rate()
303 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; in rockchip_mmc_get_clk()
319 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
399 return DIV_TO_RATE(OSC_HZ, div); in rk3128_saradc_get_clk()
406 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3128_saradc_set_clk()
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| D | clk_rk322x.c | 30 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
32 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
33 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
194 return OSC_HZ; in rkclk_pll_get_rate()
235 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; in rockchip_mmc_get_clk()
286 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
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| D | clk_rk3288.c | 133 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
134 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
149 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
228 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; in pll_para_config()
509 return OSC_HZ; in rkclk_pll_get_rate()
555 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; in rockchip_mmc_get_clk()
570 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
681 return DIV_TO_RATE(OSC_HZ, div); in rockchip_saradc_get_clk()
688 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_saradc_set_clk()
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| D | clk_rk3328.c | 34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
241 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
461 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk3328_mmc_get_clk()
490 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3328_mmc_set_clk()
535 return DIV_TO_RATE(OSC_HZ, div); in rk3328_saradc_get_clk()
542 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3328_saradc_set_clk()
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| D | clk_rk3188.c | 74 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
75 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
91 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
242 return OSC_HZ; in rkclk_pll_get_rate()
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| D | clk_rk3399.c | 46 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
294 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
336 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config()
684 return DIV_TO_RATE(OSC_HZ, div); in rk3399_mmc_get_clk()
704 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3399_mmc_set_clk()
813 return DIV_TO_RATE(OSC_HZ, div); in rk3399_saradc_get_clk()
820 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3399_saradc_set_clk()
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | cru_rk3328.h | 49 #define OSC_HZ (24 * MHz) macro
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| D | cru_rv1108.h | 11 #define OSC_HZ (24 * 1000 * 1000) macro
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| D | cru_rk3188.h | 8 #define OSC_HZ (24 * 1000 * 1000) macro
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| D | cru_rk3399.h | 71 #define OSC_HZ (24*MHz) macro
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| D | cru_rk3036.h | 10 #define OSC_HZ (24 * 1000 * 1000) macro
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| D | cru_rk3128.h | 12 #define OSC_HZ (24 * MHz) macro
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| D | cru_rk322x.h | 11 #define OSC_HZ (24 * MHz) macro
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| D | cru_rk3288.h | 11 #define OSC_HZ (24 * 1000 * 1000) macro
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