Searched refs:OUT_BATCH_REGVAL (Results 1 – 4 of 4) sorted by relevance
/external/mesa3d/src/mesa/drivers/dri/r200/ |
D | r200_blit.c | 101 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, 0); in emit_vtx_state() 103 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); in emit_vtx_state() 105 OUT_BATCH_REGVAL(R200_SE_VAP_CNTL, (R200_VAP_FORCE_W_TO_ONE | in emit_vtx_state() 107 OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL, 0); in emit_vtx_state() 108 OUT_BATCH_REGVAL(R200_SE_VTE_CNTL, 0); in emit_vtx_state() 109 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0, R200_VTX_XY); in emit_vtx_state() 110 OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); in emit_vtx_state() 111 OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | in emit_vtx_state() 168 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | in emit_tx_setup() 170 OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | in emit_tx_setup() [all …]
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D | radeon_cmdbuf.h | 88 #define OUT_BATCH_REGVAL(reg, val) \ macro
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
D | radeon_blit.c | 95 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, 0); in emit_vtx_state() 97 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); in emit_vtx_state() 100 OUT_BATCH_REGVAL(RADEON_SE_COORD_FMT, (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | in emit_vtx_state() 102 OUT_BATCH_REGVAL(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0); in emit_vtx_state() 103 OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | in emit_vtx_state() 135 OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); in emit_tx_setup() 136 OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0, (RADEON_COLOR_ARG_A_ZERO | in emit_tx_setup() 141 OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0, (RADEON_ALPHA_ARG_A_ZERO | in emit_tx_setup() 146 OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0, (RADEON_CLAMP_S_CLAMP_LAST | in emit_tx_setup() 150 OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_0, txformat); in emit_tx_setup() [all …]
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D | radeon_cmdbuf.h | 88 #define OUT_BATCH_REGVAL(reg, val) \ macro
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