| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 335 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand() local
336 bool isSub = OffImm < 0; in printThumbLdrLabelOperand()
339 if (OffImm == INT32_MIN) in printThumbLdrLabelOperand()
340 OffImm = 0; in printThumbLdrLabelOperand()
342 O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">"); in printThumbLdrLabelOperand()
344 O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">"); in printThumbLdrLabelOperand()
965 int32_t OffImm = (int32_t)MO.getImm() << scale; in printAdrLabelOperand() local
968 if (OffImm == INT32_MIN) in printAdrLabelOperand()
970 else if (OffImm < 0) in printAdrLabelOperand()
971 O << "#-" << -OffImm; in printAdrLabelOperand()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 323 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand() local
324 bool isSub = OffImm < 0; in printThumbLdrLabelOperand()
327 if (OffImm == INT32_MIN) in printThumbLdrLabelOperand()
328 OffImm = 0; in printThumbLdrLabelOperand()
330 O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">"); in printThumbLdrLabelOperand()
332 O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">"); in printThumbLdrLabelOperand()
1081 int32_t OffImm = (int32_t)MO.getImm() << scale; in printAdrLabelOperand() local
1084 if (OffImm == INT32_MIN) in printAdrLabelOperand()
1086 else if (OffImm < 0) in printAdrLabelOperand()
1087 O << "#-" << -OffImm; in printAdrLabelOperand()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 848 int32_t OffImm = (int32_t)MO2.getImm(); in printAddrModeImm12Operand() local
849 bool isSub = OffImm < 0; in printAddrModeImm12Operand()
851 if (OffImm == INT32_MIN) in printAddrModeImm12Operand()
852 OffImm = 0; in printAddrModeImm12Operand()
854 O << ", #-" << -OffImm; in printAddrModeImm12Operand()
855 else if (OffImm > 0) in printAddrModeImm12Operand()
856 O << ", #" << OffImm; in printAddrModeImm12Operand()
868 int32_t OffImm = (int32_t)MO2.getImm(); in printT2AddrModeImm8Operand() local
870 if (OffImm == INT32_MIN) in printT2AddrModeImm8Operand()
872 else if (OffImm < 0) in printT2AddrModeImm8Operand()
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| /external/capstone/arch/ARM/ |
| D | ARMInstPrinter.c | 796 int32_t OffImm; in printThumbLdrLabelOperand() local
800 OffImm = (int32_t)MCOperand_getImm(MO1); in printThumbLdrLabelOperand()
801 isSub = OffImm < 0; in printThumbLdrLabelOperand()
804 if (OffImm == INT32_MIN) in printThumbLdrLabelOperand()
805 OffImm = 0; in printThumbLdrLabelOperand()
807 SStream_concat(O, "#-0x%x", -OffImm); in printThumbLdrLabelOperand()
809 if (OffImm > HEX_THRESHOLD) in printThumbLdrLabelOperand()
810 SStream_concat(O, "#0x%x", OffImm); in printThumbLdrLabelOperand()
812 SStream_concat(O, "#%u", OffImm); in printThumbLdrLabelOperand()
822 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; in printThumbLdrLabelOperand()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1096 int OffImm = getMemoryOpOffset(MI); in FixInvalidRegPairOp() local
1100 if (OddRegNum > EvenRegNum && OffImm == 0) { in FixInvalidRegPairOp()
1127 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1128 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1136 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc, in FixInvalidRegPairOp()
1141 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, in FixInvalidRegPairOp()
1153 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, in FixInvalidRegPairOp()
1158 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc, in FixInvalidRegPairOp()
1546 int OffImm = getMemoryOpOffset(Op0); in CanFormLdStDWord() local
1549 if (OffImm >= Limit || (OffImm <= -Limit) || (OffImm & (Scale-1))) in CanFormLdStDWord()
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| D | ARMISelDAGToDAG.cpp | 114 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
163 SDValue &OffImm);
165 SDValue &OffImm);
167 SDValue &OffImm);
169 SDValue &OffImm);
170 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
175 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
177 SDValue &OffImm);
179 SDValue &OffImm);
443 SDValue &OffImm) { in SelectAddrModeImm12() argument
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| D | ARMBaseInstrInfo.cpp | 157 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); in convertToThreeAddress() local
164 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
165 unsigned Amt = ARM_AM::getAM2Offset(OffImm); in convertToThreeAddress()
176 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
190 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
191 unsigned Amt = ARM_AM::getAM3Offset(OffImm); in convertToThreeAddress()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 80 bool SelectAddrModeIndexed7S8(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S8() argument
81 return SelectAddrModeIndexed7S(N, 1, Base, OffImm); in SelectAddrModeIndexed7S8()
83 bool SelectAddrModeIndexed7S16(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S16() argument
84 return SelectAddrModeIndexed7S(N, 2, Base, OffImm); in SelectAddrModeIndexed7S16()
86 bool SelectAddrModeIndexed7S32(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S32() argument
87 return SelectAddrModeIndexed7S(N, 4, Base, OffImm); in SelectAddrModeIndexed7S32()
89 bool SelectAddrModeIndexed7S64(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S64() argument
90 return SelectAddrModeIndexed7S(N, 8, Base, OffImm); in SelectAddrModeIndexed7S64()
92 bool SelectAddrModeIndexed7S128(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S128() argument
93 return SelectAddrModeIndexed7S(N, 16, Base, OffImm); in SelectAddrModeIndexed7S128()
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| D | AArch64InstructionSelector.cpp | 1602 MachineOperand &OffImm = RootDef->getOperand(2); in selectAddrModeUnscaled() local
1603 if (!OffImm.isReg()) in selectAddrModeUnscaled()
1605 MachineInstr *RHS = MRI.getVRegDef(OffImm.getReg()); in selectAddrModeUnscaled()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 79 bool SelectAddrModeIndexed7S8(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S8() argument
80 return SelectAddrModeIndexed7S(N, 1, Base, OffImm); in SelectAddrModeIndexed7S8()
82 bool SelectAddrModeIndexed7S16(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S16() argument
83 return SelectAddrModeIndexed7S(N, 2, Base, OffImm); in SelectAddrModeIndexed7S16()
85 bool SelectAddrModeIndexed7S32(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S32() argument
86 return SelectAddrModeIndexed7S(N, 4, Base, OffImm); in SelectAddrModeIndexed7S32()
88 bool SelectAddrModeIndexed7S64(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S64() argument
89 return SelectAddrModeIndexed7S(N, 8, Base, OffImm); in SelectAddrModeIndexed7S64()
91 bool SelectAddrModeIndexed7S128(SDValue N, SDValue &Base, SDValue &OffImm) { in SelectAddrModeIndexed7S128() argument
92 return SelectAddrModeIndexed7S(N, 16, Base, OffImm); in SelectAddrModeIndexed7S128()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1651 int OffImm = getMemoryOpOffset(*MI); in FixInvalidRegPairOp() local
1655 if (OddRegNum > EvenRegNum && OffImm == 0) { in FixInvalidRegPairOp()
1681 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1682 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1686 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1687 : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1692 InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill, in FixInvalidRegPairOp()
1694 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill, in FixInvalidRegPairOp()
1707 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill, in FixInvalidRegPairOp()
1709 InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill, in FixInvalidRegPairOp()
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| D | ARMISelDAGToDAG.cpp | 102 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
135 SDValue &OffImm);
137 SDValue &OffImm);
139 SDValue &OffImm);
141 SDValue &OffImm);
142 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
145 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
147 SDValue &OffImm);
149 SDValue &OffImm);
152 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
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| D | ARMBaseInstrInfo.cpp | 179 unsigned OffImm = MI.getOperand(NumOps - 2).getImm(); in convertToThreeAddress() local
184 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
185 unsigned Amt = ARM_AM::getAM2Offset(OffImm); in convertToThreeAddress()
198 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
218 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
219 unsigned Amt = ARM_AM::getAM3Offset(OffImm); in convertToThreeAddress()
591 unsigned OffImm = Opc.getImm(); in isLdstScaledReg() local
592 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift; in isLdstScaledReg()
599 unsigned OffImm = Opc.getImm(); in isLdstScaledRegNotPlusLsl2() local
601 bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add; in isLdstScaledRegNotPlusLsl2()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1609 int OffImm = getMemoryOpOffset(*MI); in FixInvalidRegPairOp() local
1613 if (OddRegNum > EvenRegNum && OffImm == 0) { in FixInvalidRegPairOp()
1639 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1640 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1644 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1645 : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1653 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2, in FixInvalidRegPairOp()
1657 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, in FixInvalidRegPairOp()
1672 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, in FixInvalidRegPairOp()
1676 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2, in FixInvalidRegPairOp()
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| D | ARMISelDAGToDAG.cpp | 106 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
157 SDValue &OffImm);
159 SDValue &OffImm);
161 SDValue &OffImm);
163 SDValue &OffImm);
164 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
167 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
169 SDValue &OffImm);
171 SDValue &OffImm);
174 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
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| D | ARMBaseInstrInfo.cpp | 155 unsigned OffImm = MI.getOperand(NumOps - 2).getImm(); in convertToThreeAddress() local
160 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
161 unsigned Amt = ARM_AM::getAM2Offset(OffImm); in convertToThreeAddress()
175 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
197 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; in convertToThreeAddress()
198 unsigned Amt = ARM_AM::getAM3Offset(OffImm); in convertToThreeAddress()
|