| /external/capstone/arch/XCore/ |
| D | XCoreDisassembler.c | 626 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
632 S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6); in DecodeL6RInstruction()
640 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL6RInstruction()
667 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
673 S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5); in DecodeL5RInstruction()
681 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL5RInstruction()
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| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL6RInstruction()
682 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL5RInstruction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; in DecodeL6RInstruction() local
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); in DecodeL6RInstruction()
660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL6RInstruction()
682 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); in DecodeL5RInstruction()
695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); in DecodeL5RInstruction()
|
| /external/grpc-grpc/include/grpcpp/impl/codegen/ |
| D | call.h | 617 class Op5 = CallNoOp<5>, class Op6 = CallNoOp<6>>
623 public Op5,
632 this->Op5::AddOp(ops, nops); in FillOps()
643 this->Op5::FinishOp(status); in FinalizeResult()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5555 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm() local
5560 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
5563 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
5565 Op5.isImm() && !Op5.isImm0_508s4()); in tryConvertingToTwoOperandForm()
5586 const ARMOperand *LastOp = &Op5; in tryConvertingToTwoOperandForm()
5588 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && in tryConvertingToTwoOperandForm()
5614 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5764 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm() local
5769 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
5772 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
5774 Op5.isImm() && !Op5.isImm0_508s4()); in tryConvertingToTwoOperandForm()
5795 const ARMOperand *LastOp = &Op5; in tryConvertingToTwoOperandForm()
5797 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && in tryConvertingToTwoOperandForm()
5823 std::swap(Op4, Op5); in tryConvertingToTwoOperandForm()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 714 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1008 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 1156 SDValue Op3, SDValue Op4, SDValue Op5);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 4744 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
4745 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5789 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
5790 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 6966 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
6967 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2287 SDValue Op5 = Op.getOperand(5); in LowerMEMBARRIER() local
2288 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0; in LowerMEMBARRIER()
|
| /external/toolchain-utils/android_bench_suite/panorama_input/ |
| D | test_011.ppm | 7741 …Ie7C_1>Z-8T'<X*:V('FBa0Ji6;Z'7Y'/Q *J'F0L =Y,ToBeR[{Hg�Sf�PWzAQu8Y}AVw<Op5=_#1S-O;] 8^Bg#Ho…
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| D | test_008.ppm | 7035 …Ci?fHn!Mt(Hn"Ad Ru.Z<X}:Su7Su7Wx;?a#:[ Hi,Y{;Jl,Df&Pq1Op3Rt6Ik-Fh*Rt6Xz<Op5]~Cd�HTs8l�RTq;[|D]}…
|
| /external/honggfuzz/examples/apache-httpd/corpus_http1/ |
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