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Searched refs:OpIdx (Results 1 – 25 of 167) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp71 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
77 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
83 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
89 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
95 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
102 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
114 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp62 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
68 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
74 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
80 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
116 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp94 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
98 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
105 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
116 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
121 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
126 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
132 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
138 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
144 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp186 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints() argument
190 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); in getRegBankFromConstraints()
223 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) { in getInstrMappingImpl() local
224 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
243 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI); in getInstrMappingImpl()
273 Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank); in getInstrMappingImpl()
288 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) { in getInstrMappingImpl() local
289 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
296 ->getOperandMapping(OpIdx) in getInstrMappingImpl()
300 Mapping.setOperandMapping(OpIdx, RegSize, *RegBank); in getInstrMappingImpl()
[all …]
DRegBankSelect.cpp365 for (unsigned OpIdx = 0, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; in computeMapping() local
366 ++OpIdx) { in computeMapping()
367 const MachineOperand &MO = MI.getOperand(OpIdx); in computeMapping()
373 DEBUG(dbgs() << "Opd" << OpIdx); in computeMapping()
375 InstrMapping.getOperandMapping(OpIdx); in computeMapping()
384 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, in computeMapping()
391 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert)); in computeMapping()
482 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local
483 MachineOperand &MO = MI.getOperand(OpIdx); in applyMapping()
485 InstrMapping.getOperandMapping(OpIdx); in applyMapping()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc775 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
799 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
823 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp101 unsigned OpIdx);
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { in getMachineOpValue()
153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue()
239 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) in getLdStmModeOpValue()
241 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) in getLdStSORegOpValue()
269 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode2OpValue()
271 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode2OffsetOpValue()
273 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) in getPostIdxRegOpValue()
275 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode3OffsetOpValue()
922 unsigned OpIdx) { in getMachineSoRegOpValue() argument
[all …]
DARMExpandPseudoInsts.cpp419 unsigned OpIdx = 0; in ExpandVLD() local
421 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
422 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
433 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
436 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
437 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
440 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
447 SrcOpIdx = OpIdx++; in ExpandVLD()
450 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
451 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Analysis/
DConstantsScanner.h28 unsigned OpIdx; // Operand index variable
33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() && in isAtConstant()
35 return isa<Constant>(InstI->getOperand(OpIdx)); in isAtConstant()
39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) { in constant_iterator()
47 : InstI(inst_end(F)), OpIdx(0) { in constant_iterator()
50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx &&
56 return cast<Constant>(InstI->getOperand(OpIdx));
61 ++OpIdx;
64 while (OpIdx < NumOperands && !isAtConstant()) {
65 ++OpIdx;
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
930 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
934 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
938 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp112 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints() argument
116 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); in getRegBankFromConstraints()
179 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; in getInstrMappingImpl() local
180 ++OpIdx) { in getInstrMappingImpl()
181 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
200 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI); in getInstrMappingImpl()
218 OperandsMapping[OpIdx] = ValMapping; in getInstrMappingImpl()
408 for (unsigned OpIdx = 0, in applyDefaultMapping() local
410 OpIdx != EndIdx; ++OpIdx) { in applyDefaultMapping()
411 LLVM_DEBUG(dbgs() << "OpIdx " << OpIdx); in applyDefaultMapping()
[all …]
DCallLowering.cpp62 void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx, in setArgFlags() argument
66 if (Attrs.hasAttribute(OpIdx, Attribute::ZExt)) in setArgFlags()
68 if (Attrs.hasAttribute(OpIdx, Attribute::SExt)) in setArgFlags()
70 if (Attrs.hasAttribute(OpIdx, Attribute::InReg)) in setArgFlags()
72 if (Attrs.hasAttribute(OpIdx, Attribute::StructRet)) in setArgFlags()
74 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftSelf)) in setArgFlags()
76 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftError)) in setArgFlags()
78 if (Attrs.hasAttribute(OpIdx, Attribute::ByVal)) in setArgFlags()
80 if (Attrs.hasAttribute(OpIdx, Attribute::InAlloca)) in setArgFlags()
89 if (FuncInfo.getParamAlignment(OpIdx - 2)) in setArgFlags()
[all …]
DRegBankSelect.cpp414 for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands(); in computeMapping() local
415 OpIdx != EndOpIdx; ++OpIdx) { in computeMapping()
416 const MachineOperand &MO = MI.getOperand(OpIdx); in computeMapping()
422 LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n'); in computeMapping()
424 InstrMapping.getOperandMapping(OpIdx); in computeMapping()
433 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, in computeMapping()
440 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert)); in computeMapping()
541 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local
542 MachineOperand &MO = MI.getOperand(OpIdx); in applyMapping()
544 InstrMapping.getOperandMapping(OpIdx); in applyMapping()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc602 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
607 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
630 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
635 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h88 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
94 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
120 << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx in executeMatchTable()
186 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
192 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
196 << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", " in executeMatchTable()
408 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
419 << ", OpIdx=" << OpIdx << ")\n"); in executeMatchTable()
422 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
457 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
875 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DBreakFalseDeps.cpp82 bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
87 bool shouldBreakDependence(MachineInstr *, unsigned OpIdx, unsigned Pref);
108 bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, in pickBestRegisterForUndef() argument
110 MachineOperand &MO = MI->getOperand(OpIdx); in pickBestRegisterForUndef()
127 TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF); in pickBestRegisterForUndef()
164 bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence() argument
166 unsigned reg = MI->getOperand(OpIdx).getReg(); in shouldBreakDependence()
220 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local
227 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) in processUndefReads()
228 TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI); in processUndefReads()
[all …]
DMachineInstr.cpp606 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx() argument
609 assert(OpIdx < getNumOperands() && "OpIdx out of range"); in findInlineAsmFlagIdx()
612 if (OpIdx < InlineAsm::MIOp_FirstOperand) in findInlineAsmFlagIdx()
624 if (i + NumOps > OpIdx) { in findInlineAsmFlagIdx()
650 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() argument
659 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); in getRegClassConstraint()
661 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint()
666 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
667 OpIdx = DefIdx; in getRegClassConstraint()
670 int FlagIdx = findInlineAsmFlagIdx(OpIdx); in getRegClassConstraint()
[all …]
/external/llvm/utils/TableGen/
DCodeEmitterGen.cpp86 unsigned OpIdx; in AddCodeToMergeInOperand() local
87 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
89 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
90 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
113 OpIdx = NumberedOp++; in AddCodeToMergeInOperand()
116 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
127 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in AddCodeToMergeInOperand()
133 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in AddCodeToMergeInOperand()
192 unsigned OpIdx; in getInstructionCase() local
193 if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) in getInstructionCase()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeEmitterGen.cpp97 unsigned OpIdx; in AddCodeToMergeInOperand() local
98 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
100 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
101 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
124 OpIdx = NumberedOp++; in AddCodeToMergeInOperand()
127 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
138 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in AddCodeToMergeInOperand()
144 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in AddCodeToMergeInOperand()
200 unsigned OpIdx; in getInstructionCase() local
201 if (!CGI.Operands.hasOperandNamed(RV.getName(), OpIdx)) in getInstructionCase()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64AddressTypePromotion.cpp208 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { in shouldSExtOperand() argument
209 return !(isa<SelectInst>(Inst) && OpIdx == 0); in shouldSExtOperand()
311 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx; in propagateSignExtension() local
312 ++OpIdx) { in propagateSignExtension()
313 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n'); in propagateSignExtension()
314 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() || in propagateSignExtension()
315 !shouldSExtOperand(Inst, OpIdx)) { in propagateSignExtension()
320 Value *Opnd = Inst->getOperand(OpIdx); in propagateSignExtension()
323 Inst->setOperand(OpIdx, ConstantInt::getSigned(SExt->getType(), in propagateSignExtension()
330 Inst->setOperand(OpIdx, UndefValue::get(SExt->getType())); in propagateSignExtension()
[all …]
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeEmitterGen.cpp107 unsigned OpIdx; in AddCodeToMergeInOperand() local
108 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
110 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
111 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
118 OpIdx = NumberedOp++; in AddCodeToMergeInOperand()
121 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
132 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in AddCodeToMergeInOperand()
139 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in AddCodeToMergeInOperand()
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp403 unsigned OpIdx = 0; in ExpandVLD() local
405 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
406 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
422 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
425 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
432 SrcOpIdx = OpIdx++; in ExpandVLD()
435 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
436 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
[all …]

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