Searched refs:PAD_CTL_DSE_3P3V_49OHM (Results 1 – 6 of 6) sorted by relevance
28 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \31 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)34 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)37 PAD_CTL_DSE_3P3V_49OHM)40 (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)42 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)45 (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)47 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
34 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \40 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)43 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)46 PAD_CTL_DSE_3P3V_49OHM)48 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)50 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
28 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \34 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)37 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
41 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \96 #define ENET_PAD_CTRL (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM)
31 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
119 #define PAD_CTL_DSE_3P3V_49OHM (0x1<<0) macro