Searched refs:PAD_CTL_SRE_SLOW (Results 1 – 19 of 19) sorted by relevance
15 #define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \21 #define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \27 #define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \39 PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
22 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \53 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \57 PAD_CTL_SRE_SLOW)
34 PAD_CTL_PUE | PAD_CTL_SRE_SLOW)
30 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
43 PAD_CTL_SRE_SLOW \145 PAD_CTL_SRE_SLOW \195 PAD_CTL_SRE_SLOW \205 PAD_CTL_SRE_SLOW \
89 PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)90 #define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)105 #define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
33 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \36 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
124 #define PAD_CTL_SRE_SLOW (0x1 << 2) macro226 #define PAD_CTL_SRE_SLOW (0 << 0) macro
31 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \39 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
85 #define PAD_CTL_SRE_SLOW (1 << 2) macro
57 PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW)); in setup_iomux_lcd()
37 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \48 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
70 PAD_CTL_SRE_SLOW)74 PAD_CTL_SRE_SLOW)78 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
71 PAD_CTL_SRE_SLOW)75 PAD_CTL_SRE_SLOW)79 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
61 PAD_CTL_SRE_SLOW)65 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
42 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
30 PAD_CTL_SRE_SLOW)
282 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
124 PAD_CTL_SRE_SLOW = 0x0 << 0, enumerator