Home
last modified time | relevance | path

Searched refs:PHY_CON0_CTRL_DDR_MODE_SHIFT (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Ddmc_init_ddr3.c492 val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
493 val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
497 val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
498 val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
/external/u-boot/arch/arm/mach-exynos/include/mach/
Ddmc.h465 #define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 macro