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Searched refs:PHY_CON10_CTRL_OFFSETR3 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/include/mach/
Ddmc.h472 #define PHY_CON10_CTRL_OFFSETR3 (1 << 24) macro
/external/u-boot/arch/arm/mach-exynos/
Ddmc_init_ddr3.c293 setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
294 clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()