Searched refs:PLL0 (Results 1 – 3 of 3) sorted by relevance
493 tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */ in tegra_dc_sor_power_up()513 tegra_sor_write_field(sor, PLL0, in tegra_dc_sor_power_up()560 DUMP_REG(PLL0); in dump_sor_reg()707 tegra_sor_writel(sor, PLL0, in tegra_dc_sor_enable_dp()
221 #define PLL0 0x17 macro
17 ; This section allows setting the PLL0 system clock with a