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Searched refs:PLLP_OUT2_RSTN_EN (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-tegra/
Dclk_rst.h283 #define PLLP_OUT2_RSTN_EN (0 << 16) macro
/external/u-boot/arch/arm/mach-tegra/
Dclock.c792 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN; in tegra30_set_up_pllp()