Searched refs:Q22 (Results 1 – 13 of 13) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 140 case AArch64::Q22: in isOdd()
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| D | AArch64RegisterInfo.td | 396 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
755 def Z22 : AArch64Reg<22, "z22", [Q22, Z22_HI]>, DwarfRegNum<[118]>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 140 case AArch64::Q22: in isOdd()
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| D | AArch64RegisterInfo.td | 377 def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1249 case AArch64::Q21: Reg = AArch64::Q22; break; in getNextVectorRegister()
1250 case AArch64::Q22: Reg = AArch64::Q23; break; in getNextVectorRegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1137 case AArch64::Q21: Reg = AArch64::Q22; break; in getNextVectorRegister()
1138 case AArch64::Q22: Reg = AArch64::Q23; break; in getNextVectorRegister()
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 260 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
440 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 301 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
625 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
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| /external/ImageMagick/MagickCore/ |
| D | enhance.c | 409 const size_t *Q22,const size_t *Q11,const size_t *Q21, in InterpolateCLAHE() argument
430 tile->height)*(y*(x*Q12[intensity]+(tile->width-x)*Q22[intensity])+ in InterpolateCLAHE()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 163 Q22 = 143,
2593 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
3842 { AArch64::Q22, 86U },
4121 { AArch64::Q22, 86U },
19336 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
19338 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
19356 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
19358 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
19360 …h64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArc…
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| D | AArch64GenAsmMatcher.inc | 10855 case AArch64::Q22: OpKind = MCK_FPR128; break;
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1879 .Case("v22", AArch64::Q22) in matchVectorRegName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2074 .Case("v22", AArch64::Q22) in MatchNeonVectorRegName()
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