Searched refs:Q31 (Results 1 – 15 of 15) sorted by relevance
| /external/libxaac/decoder/ |
| D | ixheaacd_constants.h | 50 #define Q31 2147483647 macro
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 95 case AArch64::Q31: in isOdd()
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| D | AArch64RegisterInfo.td | 405 def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
764 def Z31 : AArch64Reg<31, "z31", [Q31, Z31_HI]>, DwarfRegNum<[127]>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 95 case AArch64::Q31: in isOdd()
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| D | AArch64RegisterInfo.td | 386 def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1258 case AArch64::Q30: Reg = AArch64::Q31; break; in getNextVectorRegister()
1260 case AArch64::Q31: in getNextVectorRegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1146 case AArch64::Q30: Reg = AArch64::Q31; break; in getNextVectorRegister()
1148 case AArch64::Q31: in getNextVectorRegister()
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 262 AArch64::Q30, AArch64::Q31
442 AArch64::Q30, AArch64::Q31
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 303 AArch64::Q30, AArch64::Q31
627 AArch64::Q30, AArch64::Q31
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 172 Q31 = 152,
2593 … AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31,
3851 { AArch64::Q31, 95U },
4130 { AArch64::Q31, 95U },
19336 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
19338 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
19356 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
19358 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
19360 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
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| D | AArch64GenAsmMatcher.inc | 10864 case AArch64::Q31: OpKind = MCK_FPR128; break;
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1888 .Case("v31", AArch64::Q31) in matchVectorRegName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2083 .Case("v31", AArch64::Q31) in MatchNeonVectorRegName()
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| /external/llvm/docs/ |
| D | LangRef.rst | 3584 128 or 256-bit QPX register (``Q0-Q31``; aliases the ``F`` registers).
3586 128 or 256-bit QPX register (``Q0-Q31``), otherwise a 128-bit
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | LangRef.rst | 3826 128 or 256-bit QPX register (``Q0-Q31``; aliases the ``F`` registers).
3828 128 or 256-bit QPX register (``Q0-Q31``), otherwise a 128-bit
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