| /external/libxaac/decoder/armv7/ |
| D | ia_xheaacd_mps_reoder_mulshift_acc.s | 61 VLD1.32 {Q4, Q5}, [R2]! @LOADING values from R2 N.real_fix
71 VMULL.S32 Q5, D7, D15
77 VSHR.S64 Q5, Q5, #31
87 VSUB.I64 Q11, Q11, Q5
105 VLD1.32 {Q4, Q5}, [R2]! @LOADING values from R2 N.real_fix
115 VMULL.S32 Q5, D7, D15
126 VSHR.S64 Q5, Q5, #31
131 VSUB.I64 Q11, Q11, Q5
149 VLD1.32 {Q4, Q5}, [R2]! @LOADING values from R2 N.real_fix
159 VMULL.S32 Q5, D7, D15
[all …]
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| D | ixheaacd_esbr_cos_sin_mod_loop2.s | 76 VQSUB.S64 Q7, Q5, Q2
77 VQSUB.S64 Q8, Q2, Q5
107 VQSUB.S64 Q7, Q2, Q5
108 VQSUB.S64 Q8, Q5, Q2
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| D | ixheaacd_esbr_cos_sin_mod_loop1.s | 55 VQSUB.S64 Q1, Q5, Q2
80 VADD.I64 Q0, Q5, Q2
107 VQSUB.S64 Q1, Q5, Q2
132 VADD.I64 Q0, Q5, Q2
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| D | ia_xheaacd_mps_mulshift.s | 34 VQDMULL.S32 Q5, D2, D6
38 VUZP.32 Q5, Q7
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| D | ixheaacd_mps_synt_pre_twiddle.s | 41 VMULL.S32 Q5, D1, D3
46 VSHRN.I64 D10, Q5, #31
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| D | ixheaacd_mps_synt_post_twiddle.s | 41 VMULL.S32 Q5, D15, D3
46 VSHRN.I64 D10, Q5, #31
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| D | ixheaacd_mps_synt_post_fft_twiddle.s | 44 VMULL.S32 Q5, D2, D6
49 VSHRN.S64 D10, Q5, #31
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| D | ixheaacd_mps_synt_out_calc.s | 31 VMULL.S32 Q5, D1, D6
35 VSHRN.S64 D9, Q5, #31
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| D | ixheaacd_calc_post_twid.s | 44 VMULL.S32 Q5, D6, D2
53 VSHRN.S64 D8, Q5, #32
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| D | ixheaacd_esbr_fwd_modulation.s | 52 VQSUB.S32 Q5, Q1, Q3
90 VADD.I64 Q0, Q2, Q5
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| D | ixheaacd_overlap_add2.s | 195 VREV64.16 Q5, Q5
234 VREV64.16 Q5, Q5
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| D | ixheaacd_post_twiddle_overlap.s | 211 VLD2.32 {Q5, Q6}, [R6], R12
220 VREV64.16 Q5, Q5
399 VLD2.32 {Q5, Q6}, [R6], R12
408 VREV64.16 Q5, Q5
662 VLD2.32 {Q5, Q6}, [R6], R12
671 VREV64.16 Q5, Q5
1028 VREV64.16 Q5, Q5
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| D | ixheaacd_pre_twiddle_compute.s | 111 VREV64.16 Q5, Q4
168 VREV64.16 Q5, Q4
237 VREV64.16 Q5, Q4
334 VREV64.16 Q5, Q4
|
| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 194 VMULL.S16 Q5,D5,D0[3] @//(U-128)*C4 FOR B
206 VQSHRN.S32 D9,Q5,#13 @//D9 = (U-128)*C4>>13 4 16-BIT VALUES
220 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
224 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
261 VADDW.U8 Q8,Q5,D28 @//Q2 - HAS Y + R
265 VADDW.U8 Q11,Q5,D29 @//Q11 - HAS Y + R
325 VMULL.S16 Q5,D5,D0[3] @//(U-128)*C4 FOR B
337 VQSHRN.S32 D9,Q5,#13 @//D9 = (U-128)*C4>>13 4 16-BIT VALUES
351 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
355 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
[all …]
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| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans_32x32_a9q.s | 208 VADD.S16 Q5, Q9,Q10 @ e[k] = resi_tmp_1 + resi_tmp_2 k ->9-16 row 1 -- dual issue
216 VREV64.16 Q5, Q5 @ Rev 9-16 of e[k], row 1
219 VSWP D10, D11 @ Q5: e[16] e[15] e[14] e[13] e[12] e[11] e[10] e[9]
224 VADD.S16 Q0, Q4, Q5 @ ee[k] = e[k] + e[16-k] k->1-8 row 1
226 VSUB.S16 Q1, Q4, Q5 @ eo[k] = e[k] - e[16-k] k->1-8 row 1 -- dual issue
287 VMULL.S16 Q5,D27,D0 @g_ai2_ihevc_trans_32[12][0-4] * eeo[0-4] R1
311 VTRN.32 Q15, Q5 @R1 transpose1 -- dual issue
339 VADD.S32 Q5,Q5,Q13 @R1 add
342 VADD.S32 Q15,Q15,Q5 @R1 add
346 VMULL.S16 Q5,D2,D0 @eo[1][0-3]* R1
[all …]
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| D | ihevc_sao_edge_offset_class1.s | 142 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
145 VCLT.U8 Q7,Q5,Q4 @vcltq_u8(pu1_cur_row, pu1_top_row)
157 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
162 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
199 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
236 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
237 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
264 VMOV Q5,Q9 @pu1_cur_row = pu1_next_row
287 VCGT.U8 Q6,Q5,Q4 @vcgtq_u8(pu1_cur_row, pu1_top_row)
288 VCLT.U8 Q7,Q5,Q4 @vcltq_u8(pu1_cur_row, pu1_top_row)
[all …]
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| D | ihevc_sao_edge_offset_class1_chroma.s | 146 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
149 VCLT.U8 Q7,Q5,Q14 @vcltq_u8(pu1_cur_row, pu1_top_row)
161 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
166 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
206 VMOV Q5,Q15 @II pu1_cur_row = pu1_next_row
248 VCGT.U8 Q6,Q5,Q9 @vcgtq_u8(pu1_cur_row, pu1_top_row)
249 VCLT.U8 Q7,Q5,Q9 @vcltq_u8(pu1_cur_row, pu1_top_row)
281 VMOV Q5,Q9 @pu1_cur_row = pu1_next_row
304 VCGT.U8 Q6,Q5,Q14 @vcgtq_u8(pu1_cur_row, pu1_top_row)
305 VCLT.U8 Q7,Q5,Q14 @vcltq_u8(pu1_cur_row, pu1_top_row)
[all …]
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| D | ihevc_sao_edge_offset_class2.s | 257 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
261 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
302 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
306 …VSUB.U8 Q5,Q9,Q5 @I sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt…
308 VADD.I8 Q12,Q12,Q5 @I edge_idx = vaddq_s8(edge_idx, sign_down)
314 VNEG.S8 Q7,Q5 @I sign_up = vnegq_s8(sign_down)
384 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
394 …VSUB.U8 Q5,Q9,Q5 @III sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_…
403 VADD.I8 Q9,Q9,Q5 @III edge_idx = vaddq_s8(edge_idx, sign_down)
407 VNEG.S8 Q7,Q5 @III sign_up = vnegq_s8(sign_down)
[all …]
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| D | ihevc_resi_trans.s | 1011 VSUBL.U8 Q5,D1,D3 @Get residue 9-16 row 1
1023 VREV64.S16 Q5,Q5 @Rev row 1
1028 VADD.S16 Q8 ,Q4,Q5 @e[k] = resi_tmp_1 + resi_tmp_2 k -> 1-8 row 1
1029 VSUB.S16 Q9 ,Q4,Q5 @o[k] = resi_tmp_1 - resi_tmp_2 k ->9-16 row 1
1078 … VMULL.S16 Q5,D4,D8 @ g_ai2_ihevc_trans_16 * R1eee[0] R1eeo[0] R1eee[0] R1eeo[0]
1079 … VMLAL.S16 Q5,D6,D9 @ + g_ai2_ihevc_trans_16 * R1eee[1] R1eeo[1] R1eee[1] R1eeo[1]
1093 VZIP.S32 Q5,Q6 @3-cycle instruction
1112 VMULL.S16 Q5,D26,D0 @g_ai2_ihevc_trans_16[10][0-4] * eo[0-4] R1
1125 VTRN.32 Q5, Q7 @R1 transpose1 -- 2 cycles
1135 VADD.S32 Q5,Q5,Q1 @R1 add
[all …]
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| D | ihevc_sao_edge_offset_class3.s | 272 VCGT.U8 Q7,Q6,Q5 @vcgtq_u8(pu1_cur_row, pu1_top_row)
282 VCLT.U8 Q8,Q6,Q5 @vcltq_u8(pu1_cur_row, pu1_top_row)
317 VCGT.U8 Q5,Q6,Q9 @I vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
319 …VSUB.U8 Q5,Q9,Q5 @I sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt…
322 VADD.I8 Q9,Q9,Q5 @I edge_idx = vaddq_s8(edge_idx, sign_down)
324 VNEG.S8 Q7,Q5 @I sign_up = vnegq_s8(sign_down)
419 VCGT.U8 Q5,Q8,Q9 @III vcgtq_u8(pu1_cur_row, pu1_next_row_tmp)
428 …VSUB.U8 Q5,Q9,Q5 @III sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_…
432 VADD.I8 Q9,Q9,Q5 @III edge_idx = vaddq_s8(edge_idx, sign_down)
434 VNEG.S8 Q7,Q5 @III sign_up = vnegq_s8(sign_down)
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.td | 68 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
70 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
75 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
77 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
110 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
115 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.td | 72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
74 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
76 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
79 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
81 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
112 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
114 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
116 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
119 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
121 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
[all …]
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenCallingConv.inc | 192 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
205 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
218 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
237 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
254 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
436 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
449 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
462 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
481 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
497 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
[all …]
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| /external/fdlibm/ |
| D | s_expm1.c | 127 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ variable
187 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5))));
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| /external/libxaac/decoder/ |
| D | ixheaacd_constants.h | 31 #define Q5 32 macro
|