| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 160 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
162 ; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
165 ; HAS-SEB-SEH: seb $2, $[[R18]]
205 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
207 ; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
210 ; HAS-SEB-SEH:seb $2, $[[R18]]
250 ; ALL: and $[[R18:[0-9]+]], $[[R12]], $[[R7]]
251 ; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]]
282 ; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
284 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaCallingConv.td | 30 CCIfType<[i64], CCAssignToRegWithShadow<[R16, R17, R18, R19, R20, R21],
34 [R16, R17, R18, R19, R20, R21]>>,
|
| D | AlphaRegisterInfo.td | 56 def R18 : GPR<18, "$18">, DwarfRegNum<[18]>;
115 R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 63 def R18 : AVRReg<18, "r18">, DwarfRegNum<[18]>;
97 def R19R18 : AVRReg<18, "r19:r18", [R18, R19]>, DwarfRegNum<[18]>;
117 add R24, R25, R18, R19, R20, R21, R22, R23,
135 add R24, R25, R18, R19, R20, R21, R22, R23,
145 add R23, R22, R21, R20, R19, R18, R17, R16
|
| D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 63 def R18 : AVRReg<18, "r18">, DwarfRegNum<[18]>;
97 def R19R18 : AVRReg<18, "r19:r18", [R18, R19]>, DwarfRegNum<[18]>;
119 add R24, R25, R18, R19, R20, R21, R22, R23,
137 add R24, R25, R18, R19, R20, R21, R22, R23,
147 add R23, R22, R21, R20, R19, R18, R17, R16
|
| D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiCallingConv.td | 25 CCAssignToReg<[R6, R7, R18, R19]>>>>,
37 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
|
| D | LanaiRegisterInfo.td | 49 R6, R7, R18, R19, // registers for passing arguments
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiCallingConv.td | 25 CCAssignToReg<[R6, R7, R18, R19]>>>>,
37 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
|
| D | LanaiRegisterInfo.td | 49 R6, R7, R18, R19, // registers for passing arguments
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeBaseInfo.h | 123 case MBlaze::R18 : return 18; in getMBlazeRegisterNumbering()
188 case 18 : return MBlaze::R18; in getMBlazeRegisterFromNumbering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 51 def R18 : Core<18, "%r18">, DwarfRegNum<[18]>;
73 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 167 {PPC::R18, -56}, in getCalleeSavedSpillSlots()
246 {PPC::R18, -108}, in getCalleeSavedSpillSlots()
|
| /external/linux-kselftest/tools/testing/selftests/powerpc/stringloops/asm/ |
| D | ppc_asm.h | 19 #define R18 r18 macro
|
| /external/llvm/test/MC/Hexagon/ |
| D | dcfetch.s | 10 P3 = SP1LOOP0(#8,R18)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/ |
| D | dcfetch.s | 10 P3 = SP1LOOP0(#8,R18)
|
| /external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/ |
| D | ppc_asm.h | 14 #define R18 r18 macro
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 107 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
116 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 86 case Lanai::R18: in getLanaiRegisterNumbering()
|
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 86 case Lanai::R18: in getLanaiRegisterNumbering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 49 case R18: case X18: case F18: case V18: case CR4EQ: return 18; in getPPCRegisterNumbering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 105 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
114 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | atomic.ll | 152 ; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
153 ; CHECK: nor $[[R11:[0-9]+]], $zero, $[[R18]]
|