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Searched refs:R29 (Results 1 – 25 of 69) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonIsetDx.td42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAc…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = Double…
452 let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
508 let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in
522 let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWo…
652 let Uses = [R29], isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
666 let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewVa…
[all …]
DHexagonRegisterInfo.cpp139 Reserved.set(Hexagon::R29); in getReservedRegs()
233 return Hexagon::R29; in getStackRegister()
DHexagonRegisterInfo.td93 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
113 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>;
215 R10, R11, R29, R30, R31)> {
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dsave-crbp-ppc32svr4.ll5 ; Save R31..R29 via R0:
12 ; Set R29 back to the value of R0 from before the updates:
14 ; Save CR through R12 using R29 as the stack pointer (aligned base pointer).
Dsave-bp.ll29 ; Check for saving/restoring frame pointer (R31) and base pointer (R29)
31 ; pointer is in R29.
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaFrameLowering.cpp56 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29) in emitPrologue()
58 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29) in emitPrologue()
59 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist); in emitPrologue()
DAlphaRegisterInfo.td67 def R29 : GPR<29, "$29">, DwarfRegNum<[29]>;
120 R29, //global offset table address
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td82 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
86 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
312 let Defs = [R29], hasSideEffects = 1 in
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
383 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
DHexagonRegisterInfo.cpp145 Reserved.set(Hexagon::R29); in getReservedRegs()
316 return Hexagon::R29; in getStackRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Drdf-copy-undef.ll4 ; After a copy R20 = R29, RDF copy propagation attempted to replace R20 with
5 ; R29. R29 did not have a reaching def at that point (which isn't unusual),
6 ; but copy propagation tried to link the new use of R29 to the presumed
/external/autotest/server/site_tests/platform_RebootAfterUpdate/
Dcontrol30 gs://chromeos-image-archive/x86-alex/R29-4165.0.0
33 x86-alex/R29-4165.0.0/autotest/packages"
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp195 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
251 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
321 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) { in getDuplexCandidateGroup()
365 HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg && in getDuplexCandidateGroup()
413 if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
713 else if (Inst.getOperand(1).getReg() == Hexagon::R29) { in deriveSubInst()
865 if (Inst.getOperand(1).getReg() == Hexagon::R29) { in deriveSubInst()
921 } else if (Inst.getOperand(0).getReg() == Hexagon::R29) { in deriveSubInst()
928 if (Inst.getOperand(0).getReg() == Hexagon::R29) { in deriveSubInst()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp203 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
259 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
323 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) { in getDuplexCandidateGroup()
367 HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg && in getDuplexCandidateGroup()
415 if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
723 if (Inst.getOperand(1).getReg() == Hexagon::R29) { in deriveSubInst()
876 if (Inst.getOperand(1).getReg() == Hexagon::R29) { in deriveSubInst()
933 } else if (Inst.getOperand(0).getReg() == Hexagon::R29) { in deriveSubInst()
941 if (Inst.getOperand(0).getReg() == Hexagon::R29) { in deriveSubInst()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td74 def R29 : AVRReg<29, "r29">, DwarfRegNum<[29]>;
91 def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
139 R28, R29, R17, R16
DAVRCallingConv.td57 def CSR_Normal : CalleeSavedRegs<(add R29, R28, (sequence "R%u", 17, 2))>;
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td74 def R29 : AVRReg<29, "r29">, DwarfRegNum<[29]>;
91 def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
141 R28, R29, R17, R16
DAVRCallingConv.td64 def CSR_Normal : CalleeSavedRegs<(add R29, R28, (sequence "R%u", 17, 2))>;
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h134 case MBlaze::R29 : return 29; in getMBlazeRegisterNumbering()
199 case 29 : return MBlaze::R29; in getMBlazeRegisterFromNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td27 R21, R22, R23, R24, R25, R26, R27, R28, R29,
44 R21, R22, R23, R24, R25, R26, R27, R28, R29,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.h156 {PPC::R29, -12}, in getCalleeSavedSpillSlots()
235 {PPC::R29, -20}, in getCalleeSavedSpillSlots()
/external/linux-kselftest/tools/testing/selftests/powerpc/stringloops/asm/
Dppc_asm.h24 #define R29 r29 macro
/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/
Dppc_asm.h19 #define R29 r29 macro
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h108 case Lanai::R29: in getLanaiRegisterNumbering()
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h108 case Lanai::R29: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h60 case R29: case X29: case F29: case V29: case CR7GT: return 29; in getPPCRegisterNumbering()

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