| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaFrameLowering.cpp | 82 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) in emitPrologue()
83 .addReg(Alpha::R30); in emitPrologue()
85 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) in emitPrologue()
86 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
87 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) in emitPrologue()
88 .addImm(getLower16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); in emitPrologue()
99 .addReg(Alpha::R30).addReg(Alpha::R30); in emitPrologue()
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) in emitEpilogue()
132 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) in emitEpilogue()
[all …]
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| D | AlphaRegisterInfo.cpp | 75 Reserved.set(Alpha::R30); in getReservedRegs()
104 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) in eliminateCallFramePseudoInstr()
105 .addImm(-Amount).addReg(Alpha::R30); in eliminateCallFramePseudoInstr()
108 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) in eliminateCallFramePseudoInstr()
109 .addImm(Amount).addReg(Alpha::R30); in eliminateCallFramePseudoInstr()
149 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); in eliminateFrameIndex()
172 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); in eliminateFrameIndex()
182 return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30; in getFrameRegister()
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| D | AlphaRegisterInfo.td | 68 def R30 : GPR<30, "$30">, DwarfRegNum<[30]>;
124 R15, R30, R31)>; //zero
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIsetDx.td | 42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAc…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = Double…
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWo…
696 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
706 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
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| D | HexagonRegisterInfo.cpp | 140 Reserved.set(Hexagon::R30); in getReservedRegs()
228 return Hexagon::R30; in getFrameRegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 264 MI.getOperand(1).getReg() == Hexagon::R30) { in remapInstruction()
272 MI.getOperand(1).getReg() == Hexagon::R30) { in remapInstruction()
280 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
288 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
296 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
304 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
312 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
320 MI.getOperand(2).getReg() == Hexagon::R30) { in remapInstruction()
600 Hexagon::R30, Hexagon::R31}; in DecodeIntRegsRegisterClass()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | cfi-offset.ll | 3 ; They are all based on R30+8 which points to the pair FP/LR stored by an
6 ; R30+8.
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| D | bit-cmp0.mir | 66 # CHECK: %[[R30:[0-9]+]]:intregs = A2_tfrsi 1
67 # CHECK: $r0 = COPY %[[R30]]
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | cfi-offset.ll | 3 ; They are all based on R30+8 which points to the pair FP/LR stored by an
6 ; R30+8.
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 75 def R30 : AVRReg<30, "r30">, DwarfRegNum<[30]>;
90 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
119 R30, R31, R26, R27,
137 R30, R31, R26, R27,
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 75 def R30 : AVRReg<30, "r30">, DwarfRegNum<[30]>;
90 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
121 R30, R31, R26, R27,
139 R30, R31, R26, R27,
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeBaseInfo.h | 135 case MBlaze::R30 : return 30; in getMBlazeRegisterNumbering()
200 case 30 : return MBlaze::R30; in getMBlazeRegisterFromNumbering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPseudo.td | 82 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
86 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
248 let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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| D | HexagonRegisterInfo.cpp | 146 Reserved.set(Hexagon::R30); in getReservedRegs()
311 return Hexagon::R30; in getFrameRegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 63 def R30 : Core<30, "%r30">, DwarfRegNum<[30]>;
74 R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>;
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 28 R30, R31, R32, R33, R34, R35, R36, R37, R38,
45 R30, R31, R32, R33, R34, R35, R36, R37, R38,
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 155 {PPC::R30, -8}, in getCalleeSavedSpillSlots()
234 {PPC::R30, -12}, in getCalleeSavedSpillSlots()
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| /external/linux-kselftest/tools/testing/selftests/powerpc/stringloops/asm/ |
| D | ppc_asm.h | 25 #define R30 r30 macro
|
| /external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/ |
| D | ppc_asm.h | 20 #define R30 r30 macro
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 110 case Lanai::R30: in getLanaiRegisterNumbering()
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 110 case Lanai::R30: in getLanaiRegisterNumbering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | restore-r30.ll | 10 ; R30 should not appear in an instruction after it's been restored.
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 61 case R30: case X30: case F30: case V30: case CR7EQ: return 30; in getPPCRegisterNumbering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/ |
| D | bitcount-64b.ll | 30 ; CHECK-DAG: r[[R30:[0-9]+]] = ##134744072
32 ; CHECK: v[[V33:[0-9]+]] = vsplat(r[[R30]])
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| D | bitcount-128b.ll | 30 ; CHECK-DAG: r[[R30:[0-9]+]] = ##134744072
32 ; CHECK: v[[V33:[0-9]+]] = vsplat(r[[R30]])
|