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Searched refs:R31 (Results 1 – 25 of 81) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaLLRP.cpp77 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) in runOnMachineFunction()
78 .addReg(Alpha::R31) in runOnMachineFunction()
79 .addReg(Alpha::R31); in runOnMachineFunction()
89 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) in runOnMachineFunction()
90 .addReg(Alpha::R31) in runOnMachineFunction()
91 .addReg(Alpha::R31); in runOnMachineFunction()
92 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) in runOnMachineFunction()
93 .addReg(Alpha::R31) in runOnMachineFunction()
94 .addReg(Alpha::R31); in runOnMachineFunction()
103 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) in runOnMachineFunction()
[all …]
DAlphaInstrInfo.cpp322 BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31) in insertNoop()
323 .addReg(Alpha::R31) in insertNoop()
324 .addReg(Alpha::R31); in insertNoop()
DAlphaRegisterInfo.td69 def R31 : GPR<31, "$31">, DwarfRegNum<[31]>;
124 R15, R30, R31)>; //zero
/external/llvm/lib/Target/Hexagon/
DHexagonIsetDx.td32 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBr…
42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAc…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
122 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBran…
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = Double…
277 let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffect…
536 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPr…
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWo…
599 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBra…
[all …]
DHexagonRegisterInfo.cpp42 : HexagonGenRegisterInfo(Hexagon::R31) {} in HexagonRegisterInfo()
141 Reserved.set(Hexagon::R31); in getReservedRegs()
214 return Hexagon::R31; in getRARegister()
DHexagonRegisterInfo.td95 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
114 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
215 R10, R11, R29, R30, R31)> {
270 R28, R31,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.h121 static const SpillSlot darwinOffsets = {PPC::R31, -4}; in getCalleeSavedSpillSlots()
154 {PPC::R31, -4}, in getCalleeSavedSpillSlots()
233 {PPC::R31, -4}, in getCalleeSavedSpillSlots()
DPPCFrameLowering.cpp332 .addReg(PPC::R31) in emitPrologue()
437 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); in emitPrologue()
443 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); in emitPrologue()
459 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) in emitPrologue()
474 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : in emitPrologue()
586 .addReg(PPC::R31).addImm(FrameSize); in emitEpilogue()
595 .addReg(PPC::R31) in emitEpilogue()
649 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) in emitEpilogue()
663 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitEpilogue()
798 unsigned MinGPR = PPC::R31; in processFunctionBeforeFrameFinalized()
DPPCRegisterInfo.cpp110 PPC::R28, PPC::R29, PPC::R30, PPC::R31, in getCalleeSavedRegs()
136 PPC::R28, PPC::R29, PPC::R30, PPC::R31, in getCalleeSavedRegs()
248 Reserved.set(PPC::R31); in getReservedRegs()
271 Reserved.set(PPC::R31); in getReservedRegs()
383 .addReg(PPC::R31) in lowerDynamicAlloc()
547 PPC::R31 : PPC::R1, in eliminateFrameIndex()
634 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; in getFrameRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dsave-bp.ll14 ; Check for saving/restoring frame pointer (R31) and base pointer (R30)
29 ; Check for saving/restoring frame pointer (R31) and base pointer (R29)
Dsave-crbp-ppc32svr4.ll5 ; Save R31..R29 via R0:
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td76 def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
90 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
119 R30, R31, R26, R27,
137 R30, R31, R26, R27,
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td76 def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
90 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
121 R30, R31, R26, R27,
139 R30, R31, R26, R27,
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h136 case MBlaze::R31 : return 31; in getMBlazeRegisterNumbering()
201 case 31 : return MBlaze::R31; in getMBlazeRegisterFromNumbering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td82 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
86 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
183 Defs = [PC, R31, R6, R7, P0] in
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
383 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
DHexagonRegisterInfo.cpp46 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, in HexagonRegisterInfo()
147 Reserved.set(Hexagon::R31); in getReservedRegs()
297 return Hexagon::R31; in getRARegister()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td28 R30, R31, R32, R33, R34, R35, R36, R37, R38,
45 R30, R31, R32, R33, R34, R35, R36, R37, R38,
/external/linux-kselftest/tools/testing/selftests/powerpc/stringloops/asm/
Dppc_asm.h26 #define R31 r31 macro
/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/
Dppc_asm.h21 #define R31 r31 macro
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h112 case Lanai::R31: in getLanaiRegisterNumbering()
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h112 case Lanai::R31: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h62 case R31: case X31: case F31: case V31: case CR7UN: return 31; in getPPCRegisterNumbering()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Drotate.ll46 ; CHECK: r[[R31:[0-9]+]] = and(r1,#31)
49 ; CHECK: r[[R33]] |= lsr(r0,r[[R31]])
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp269 if (Hexagon::R31 == DstReg) { in getDuplexCandidateGroup()
288 (Hexagon::R31 == DstReg)) { in getDuplexCandidateGroup()
627 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
630 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp275 if (Hexagon::R31 == DstReg) in getDuplexCandidateGroup()
295 (Hexagon::R31 == DstReg)) { in getDuplexCandidateGroup()
630 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
633 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()

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