Searched refs:RCC_PLLNCFGR1_DIVN_MASK (Results 1 – 1 of 1) sorted by relevance
173 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) macro835 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_read_pll_freq()1338 & RCC_PLLNCFGR1_DIVN_MASK; in pll_config()