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Searched refs:REGLIST2 (Results 1 – 5 of 5) sorted by relevance

/external/swiftshader/third_party/subzero/src/
DIceRegistersARM32.def9 X(Reg_r0, 0, "r0", 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r0, r0r1)) \
10 X(Reg_r1, 1, "r1", 2, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r1, r0r1)) \
11 X(Reg_r2, 2, "r2", 3, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r2, r2r3)) \
12 X(Reg_r3, 3, "r3", 4, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r3, r2r3)) \
13 X(Reg_r4, 4, "r4", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r4, r4r5)) \
14 X(Reg_r5, 5, "r5", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r5, r4r5)) \
15 X(Reg_r6, 6, "r6", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r6, r6r7)) \
16 X(Reg_r7, 7, "r7", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r7, r6r7)) \
17 X(Reg_r8, 8, "r8", 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r8, r8r9)) \
18 X(Reg_r9, 9, "r9", 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST2(RegARM32, r9, r8r9)) \
[all …]
DIceInstX8632.def50 REGLIST2(RegX8632, eax, ax)) \
52 REGLIST2(RegX8632, ecx, cx)) \
54 REGLIST2(RegX8632, edx, dx)) \
56 REGLIST2(RegX8632, ebx, bx)) \
59 REGLIST2(RegX8632, eax, ax)) \
61 REGLIST2(RegX8632, ecx, cx)) \
63 REGLIST2(RegX8632, edx, dx)) \
65 REGLIST2(RegX8632, ebx, bx)) \
DIceRegList.h26 #define REGLIST2(ns, r0, r1) \ macro
/external/llvm/test/CodeGen/ARM/
Dmemcpy-ldm-stm.ll77 ; CHECK: ldm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST2:{.*}]]
78 ; CHECK: stm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST2]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dmemcpy-ldm-stm.ll77 ; CHECK: ldm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST2:{.*}]]
78 ; CHECK: stm{{(\.w)?}} {{[rl0-9]+!?}}, [[REGLIST2]]