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Searched refs:REGLIST3 (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/subzero/src/
DIceRegistersARM32.def28 X(Reg_r0r1, 0, "r0, r1", 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r0r1, r0, r1)) \
29 X(Reg_r2r3, 2, "r2, r3", 2, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r2r3, r2, r3)) \
30 X(Reg_r4r5, 4, "r4, r5", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r4r5, r4, r5)) \
31 X(Reg_r6r7, 6, "r6, r7", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r6r7, r6, r7)) \
32 X(Reg_r8r9, 8, "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r8r9, r8, r9)) \
33 X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r10fp, r10, fp))
37 X(Reg_s0, 0, "s0", 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s0, d0, q0)) \
38 X(Reg_s1, 1, "s1", 2, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s1, d0, q0)) \
39 X(Reg_s2, 2, "s2", 3, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s2, d1, q0)) \
40 X(Reg_s3, 3, "s3", 4, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s3, d1, q0)) \
[all …]
DIceInstX8664.def59 REGLIST3(RegX8664, rax, eax, ax)) \
61 REGLIST3(RegX8664, rcx, ecx, cx)) \
63 REGLIST3(RegX8664, rdx, edx, dx)) \
65 REGLIST3(RegX8664, r8, r8d, r8w)) \
67 REGLIST3(RegX8664, r9, r9d, r9w)) \
69 REGLIST3(RegX8664, r10, r10d, r10w)) \
71 REGLIST3(RegX8664, r11, r11d, r11w)) \
73 REGLIST3(RegX8664, rsi, esi, si)) \
75 REGLIST3(RegX8664, rdi, edi, di)) \
77 REGLIST3(RegX8664, rbx, ebx, bx)) \
[all …]
DIceInstX8632.def77 REGLIST3(RegX8632, ax, al, ah)) \
79 REGLIST3(RegX8632, cx, cl, ch)) \
81 REGLIST3(RegX8632, dx, dl, dh)) \
83 REGLIST3(RegX8632, bx, bl, bh)) \
94 REGLIST3(RegX8632, eax, al, ah)) \
96 REGLIST3(RegX8632, ecx, cl, ch)) \
98 REGLIST3(RegX8632, edx, dl, dh)) \
100 REGLIST3(RegX8632, ebx, bl, bh)) \
DIceRegList.h28 #define REGLIST3(ns, r0, r1, r2) \ macro
/external/llvm/test/CodeGen/ARM/
Dmemcpy-ldm-stm.ll79 ; CHECKV6: ldm {{r[0-7]!?}}, [[REGLIST3:{.*}]]
80 ; CHECKV6: stm {{r[0-7]!?}}, [[REGLIST3]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dmemcpy-ldm-stm.ll79 ; CHECKV6: ldm {{r[0-7]!?}}, [[REGLIST3:{.*}]]
80 ; CHECKV6: stm {{r[0-7]!?}}, [[REGLIST3]]