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Searched refs:REGNUM (Results 1 – 25 of 28) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vaddv.ll5 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
6 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
16 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
17 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
28 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
29 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
39 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
40 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
52 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
53 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
[all …]
Darm64-scvt.ll74 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
75 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
87 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
88 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
100 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
101 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
114 ; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, #8]
115 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
128 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
129 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
[all …]
Darm64-smaxv.ll5 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
6 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
16 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
17 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
28 ; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v0, v0
29 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
38 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
39 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
49 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
50 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
[all …]
Darm64-sminv.ll5 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
6 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
16 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
17 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
28 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
29 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
38 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
39 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
49 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
50 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
[all …]
Darm64-uminv.ll91 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
92 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
103 ; CHECK: uminv.4h h[[REGNUM:[0-9]+]], v1
104 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
115 ; CHECK: uminp.2s v[[REGNUM:[0-9]+]], v1, v1
116 ; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
126 ; CHECK: uminv.16b b[[REGNUM:[0-9]+]], v1
127 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
138 ; CHECK: uminv.8h h[[REGNUM:[0-9]+]], v1
139 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
[all …]
Darm64-umaxv.ll91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
92 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
103 ; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
104 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
115 ; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
116 ; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
126 ; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
127 ; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
138 ; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
139 ; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
[all …]
Darm64-vector-ldst.ll466 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
467 ; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]]
478 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
479 ; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]]
490 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
491 ; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]]
502 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
503 ; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]]
514 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
515 ; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]]
[all …]
Darm64-vaddlv.ll5 ; CHECK: saddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
6 ; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
15 ; CHECK: uaddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
16 ; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
Darm64-promote-const.ll44 ; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
46 ; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
47 ; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]]
55 ; REGULAR: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
57 ; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
58 ; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]]
/external/llvm/test/CodeGen/AArch64/
Darm64-vaddv.ll5 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
6 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
16 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
17 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
28 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
29 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
39 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
40 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
52 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
53 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
[all …]
Darm64-scvt.ll74 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
75 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
87 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
88 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
100 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
101 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
114 ; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, #8]
115 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
128 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
129 ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
[all …]
Darm64-smaxv.ll5 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
6 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
16 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
17 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
28 ; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v0, v0
29 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
38 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
39 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
49 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
50 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
[all …]
Darm64-sminv.ll5 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
6 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
16 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
17 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
28 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
29 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
38 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
39 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
49 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
50 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
[all …]
Darm64-umaxv.ll91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
92 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
103 ; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
104 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
115 ; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
116 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
126 ; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
127 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
138 ; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
139 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
[all …]
Darm64-uminv.ll91 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
92 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
103 ; CHECK: uminv.4h h[[REGNUM:[0-9]+]], v1
104 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
115 ; CHECK: uminp.2s v[[REGNUM:[0-9]+]], v1, v1
116 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
126 ; CHECK: uminv.16b b[[REGNUM:[0-9]+]], v1
127 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
138 ; CHECK: uminv.8h h[[REGNUM:[0-9]+]], v1
139 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
[all …]
Darm64-vector-ldst.ll419 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
420 ; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]]
431 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
432 ; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]]
443 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
444 ; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]]
455 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
456 ; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]]
467 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
468 ; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]]
[all …]
Darm64-vaddlv.ll5 ; CHECK: saddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
6 ; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
15 ; CHECK: uaddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
16 ; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
Darm64-promote-const.ll44 ; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
46 ; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
47 ; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]]
55 ; REGULAR: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
57 ; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
58 ; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dpic-load.ll13 ; CHECK-NOMOVT: ldr r[[REGNUM:[0-9]+]], LCPI0_0
15 ; CHECK-NOMOVT: add r[[REGNUM]], pc
16 ; CHECK-NOMOVT: ldr r1, [r[[REGNUM]]
/external/llvm/test/CodeGen/Thumb2/
Dpic-load.ll13 ; CHECK-NOMOVT: ldr r[[REGNUM:[0-9]+]], LCPI0_0
15 ; CHECK-NOMOVT: add r[[REGNUM]], pc
16 ; CHECK-NOMOVT: ldr r1, [r[[REGNUM]]
/external/u-boot/board/freescale/b4860qds/
Db4860qds_qixis.h27 #define REGNUM 0x00 macro
Deth_b4860qds.c303 qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM); in board_eth_init()
/external/u-boot/board/Barix/ipam390/
Dipam390-ais-uart.cfg143 ; REGNUM: | regNum |
147 ;REGNUM = 5
/external/u-boot/board/freescale/corenet_ds/
Deth_superhydra.c81 #define REGNUM 0x00 macro
587 qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM); in board_eth_init()
/external/llvm/test/CodeGen/ARM/
Dldrd.ll24 ; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]]

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