Searched refs:RISCVAsmBackend (Results 1 – 2 of 2) sorted by relevance
29 class RISCVAsmBackend : public MCAsmBackend { class35 RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit) in RISCVAsmBackend() function in __anon202828cb0111::RISCVAsmBackend38 ~RISCVAsmBackend() override {} in ~RISCVAsmBackend()119 bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, in fixupNeedsRelaxationAdvanced()147 void RISCVAsmBackend::relaxInstruction(const MCInst &Inst, in relaxInstruction()185 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const { in getRelaxedOpcode()199 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst, in mayNeedRelaxation()204 bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { in writeNopData()319 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, in applyFixup()347 RISCVAsmBackend::createObjectTargetWriter() const { in createObjectTargetWriter()[all …]
2 RISCVAsmBackend.cpp