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Searched refs:Rdm (Results 1 – 12 of 12) sorted by relevance

/external/vixl/test/aarch32/config/
Dcond-rd-operand-rn-shift-rs-t32.json28 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, ASR <Rs>
29 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSL <Rs>
30 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSR <Rs>
31 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, ROR <Rs>
36 "Mov", // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
37 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
38 // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
39 // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
41 "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
42 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
[all …]
Dcond-rd-rn-operand-rm-t32.json33 // MNEMONIC{<c>}.N <Rdm>, SP, <Rdm>
54 // ADD{<c>}{<q>} {<Rdm>}, SP, <Rdm> ; T1
122 "Asr", // ASR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
125 "Asrs", // ASRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
128 "Lsl", // LSL<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
131 "Lsls", // LSLS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
134 "Lsr", // LSR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
137 "Lsrs", // LSRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
140 "Ror", // ROR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
143 "Rors" // RORS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
[all …]
Dcond-rdlow-rnlow-rmlow-t32.json28 // MNEMONIC{<c>}.N <Rdm>, <Rn>, <Rdm>
32 "Mul", // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
33 "Muls" // MULS{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
77 "Muls" // MULS{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
93 "Mul" // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td1138 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1561 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1562 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1563 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1564 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1565 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1566 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb.td1212 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1697 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1698 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1699 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1700 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1701 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1702 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
/external/capstone/arch/ARM/
DARMDisassembler.c3835 unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); in DecodeThumbAddSPReg() local
3836 Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; in DecodeThumbAddSPReg()
3838 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
3841 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
DARMGenAsmWriter.inc11634 // (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)
11707 // (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)
11718 // (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)
11756 // (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, pred:$p)
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp3041 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); in DecodeThumbAddSPReg() local
3042 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; in DecodeThumbAddSPReg()
3044 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
3046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb.td1081 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp3900 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); in DecodeThumbAddSPReg() local
3901 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; in DecodeThumbAddSPReg()
3903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
3906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp3900 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); in DecodeThumbAddSPReg() local
3901 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; in DecodeThumbAddSPReg()
3903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
3906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) in DecodeThumbAddSPReg()
/external/honggfuzz/examples/apache-httpd/corpus_http1/
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