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Searched refs:Reg1Op (Results 1 – 2 of 2) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1490 const MachineOperand &Reg1Op = MI.getOperand(1); in MergeBaseUpdateLSDouble() local
1491 if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base) in MergeBaseUpdateLSDouble()
1516 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define); in MergeBaseUpdateLSDouble()
1519 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op); in MergeBaseUpdateLSDouble()
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1446 const MachineOperand &Reg1Op = MI.getOperand(1); in MergeBaseUpdateLSDouble() local
1447 if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base) in MergeBaseUpdateLSDouble()
1472 MIB.addOperand(Reg0Op).addOperand(Reg1Op) in MergeBaseUpdateLSDouble()
1477 .addOperand(Reg0Op).addOperand(Reg1Op); in MergeBaseUpdateLSDouble()