Searched refs:Reg3 (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 190 unsigned Reg3 = MI->getOperand(3).getReg(); in processBlock() local
195 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
196 && Reg3 != OldFMAReg) { in processBlock()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 191 unsigned Reg3 = MI.getOperand(3).getReg(); in processBlock() local
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
197 && Reg3 != OldFMAReg) { in processBlock()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
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| D | MipsAsmPrinter.cpp | 790 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
795 I.addOperand(MCOperand::createReg(Reg3)); in EmitInstrRegRegReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 98 unsigned Reg1, unsigned Reg2, unsigned Reg3);
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| D | MipsAsmPrinter.cpp | 845 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
850 I.addOperand(MCOperand::createReg(Reg3)); in EmitInstrRegRegReg()
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 629 CodeGenRegister *Reg3 = i2->second; in computeComposites() local
631 if (Reg2 == Reg3) in computeComposites()
636 if (i1d->second == Reg3) { in computeComposites()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.def | 30 // vmvn Reg3, Cmp? /* only if NEG_V = true */
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 219 unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, in buildEXP() argument
229 .addReg(Reg3) in buildEXP()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1140 CodeGenRegister *Reg3 = i2->second; in computeComposites() local
1142 if (Reg2 == Reg3) in computeComposites()
1145 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); in computeComposites()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1335 CodeGenRegister *Reg3 = i2->second; in computeComposites() local
1337 if (Reg2 == Reg3) in computeComposites()
1340 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); in computeComposites()
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