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Searched refs:RegBytes (Results 1 – 8 of 8) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp3277 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad() local
3278 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; in expandUnalignedLoad()
3290 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedLoad()
3291 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedLoad()
3306 Offset += RegBytes; in expandUnalignedLoad()
3438 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore() local
3439 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; in expandUnalignedStore()
3451 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedStore()
3452 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedStore()
3468 Offset += RegBytes; in expandUnalignedStore()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp1968 int RegBytes = TRI->getRegSizeInBits(*RC) / 8; in canHardenRegister() local
1969 if (RegBytes > 8) in canHardenRegister()
1983 if (RC == NOREXRegClasses[Log2_32(RegBytes)]) in canHardenRegister()
1989 return RC->hasSuperClassEq(GPRRegClasses[Log2_32(RegBytes)]); in canHardenRegister()
DX86InstrInfo.h84 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
DX86InstrInfo.cpp2353 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes, in getCMovFromCond() argument
2392 switch(RegBytes) { in getCMovFromCond()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp4016 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad() local
4017 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; in expandUnalignedLoad()
4029 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedLoad()
4030 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedLoad()
4044 Offset += RegBytes; in expandUnalignedLoad()
4171 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore() local
4172 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; in expandUnalignedStore()
4185 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedStore()
4186 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedStore()
4202 Offset += RegBytes; in expandUnalignedStore()
/external/llvm/lib/Target/X86/
DX86InstrInfo.h72 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
DX86InstrInfo.cpp3880 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes, in getCMovFromCond() argument
3919 switch(RegBytes) { in getCMovFromCond()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp411 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedStore() local
412 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; in ExpandUnalignedStore()
421 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); in ExpandUnalignedStore()
437 Offset += RegBytes; in ExpandUnalignedStore()
523 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedLoad() local
524 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; in ExpandUnalignedLoad()
529 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); in ExpandUnalignedLoad()
545 Offset += RegBytes; in ExpandUnalignedLoad()