Searched refs:RegExcess (Results 1 – 5 of 5) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | GCNSchedStrategy.cpp | 227 if (TopCand.Reason == RegExcess && TopCand.RPDelta.Excess.getUnitInc() <= 0) { in pickNodeBidirectional()
229 } else if (BotCand.Reason == RegExcess && BotCand.RPDelta.Excess.getUnitInc() <= 0) { in pickNodeBidirectional()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineScheduler.h | 765 NoCand, Only1, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineScheduler.h | 790 NoCand, Only1, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 2477 case RegExcess: return "REG-EXCESS"; in getReasonStr()
2502 case RegExcess: in traceCandidate()
2898 TryCand, Cand, RegExcess, TRI, in tryCandidate()
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| /external/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 2397 case RegExcess: return "REG-EXCESS"; in getReasonStr()
2422 case RegExcess: in traceCandidate()
2812 TryCand, Cand, RegExcess, TRI, in tryCandidate()
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