Searched refs:RegID (Results 1 – 7 of 7) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| D | RegisterFile.cpp | 145 unsigned RegID = WS.getRegisterID(); in addRegisterWrite() local
146 assert(RegID && "Adding an invalid register definition?"); in addRegisterWrite()
150 << ", " << MRI.getName(RegID) << "]\n"; in addRegisterWrite()
166 const RegisterRenamingInfo &RRI = RegisterMappings[RegID].second; in addRegisterWrite()
167 if (RRI.RenameAs && RRI.RenameAs != RegID) { in addRegisterWrite()
168 RegID = RRI.RenameAs; in addRegisterWrite()
169 const WriteRef &OtherWrite = RegisterMappings[RegID].first; in addRegisterWrite()
185 RegisterMappings[RegID].first = Write; in addRegisterWrite()
186 for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) in addRegisterWrite()
193 allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs); in addRegisterWrite()
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| D | InstrBuilder.cpp | 412 int RegID = -1; in createInstruction() local
419 RegID = Op.getReg(); in createInstruction()
422 RegID = RD.RegisterID; in createInstruction()
426 if (!RegID) in createInstruction()
430 assert(RegID > 0 && "Invalid register ID found!"); in createInstruction()
431 NewIS->getUses().emplace_back(llvm::make_unique<ReadState>(RD, RegID)); in createInstruction()
453 unsigned RegID = WD.isImplicitWrite() ? WD.RegisterID in createInstruction() local
456 if (WD.IsOptionalDef && !RegID) { in createInstruction()
461 assert(RegID && "Expected a valid register ID!"); in createInstruction()
463 WD, RegID, /* ClearsSuperRegs */ WriteMask[WriteIndex])); in createInstruction()
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| D | Instruction.h | 119 WriteState(const WriteDescriptor &Desc, unsigned RegID,
121 : WD(Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID), in WD()
173 ReadState(const ReadDescriptor &Desc, unsigned RegID) in ReadState() argument
174 : RD(Desc), RegisterID(RegID), DependentWrites(0), in ReadState()
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| D | RegisterFile.h | 160 unsigned RegID) const;
161 void updateOnRead(ReadState &RS, unsigned RegID);
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| D | DispatchStage.h | 80 unsigned RegID) const { in collectWrites() argument
81 return PRF.collectWrites(Vec, RegID); in collectWrites()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 405 auto ClearsSuperReg = [=](unsigned RegID) { in clearsSuperRegisters() argument
410 if (GR32RC.contains(RegID)) in clearsSuperRegisters()
421 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID); in clearsSuperRegisters()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 4773 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ? in LowerINTRINSIC_WO_CHAIN() local
4775 return getPreloadedValue(DAG, *MFI, VT, RegID); in LowerINTRINSIC_WO_CHAIN()
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