Searched refs:RegPairOdd (Results 1 – 9 of 9) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 298 case ARMRI::RegPairOdd: in getRegAllocationHints()
342 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || in updateRegAllocHint()
356 Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven in updateRegAllocHint()
357 : ARMRI::RegPairOdd, OtherReg); in updateRegAllocHint()
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| D | ARMBaseRegisterInfo.h | 36 RegPairOdd = 1, enumerator
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| D | ARMLoadStoreOptimizer.cpp | 2317 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 269 case ARMRI::RegPairOdd: in getRegAllocationHints()
314 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || in updateRegAllocHint()
328 Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven in updateRegAllocHint()
329 : ARMRI::RegPairOdd, OtherReg); in updateRegAllocHint()
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| D | ARMBaseRegisterInfo.h | 27 RegPairOdd = 1, enumerator
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| D | ARMLoadStoreOptimizer.cpp | 2271 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 31 RegPairOdd = 1, enumerator
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| D | ARMBaseRegisterInfo.cpp | 523 } else if (HintType == ARMRI::RegPairOdd) { in getRawAllocationOrder()
558 else if (Type == (unsigned)ARMRI::RegPairOdd) in ResolveRegAllocHint()
572 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || in UpdateRegAllocHint()
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| D | ARMLoadStoreOptimizer.cpp | 1714 MRI->setRegAllocationHint(OddReg, ARMRI::RegPairOdd, EvenReg); in RescheduleOps()
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