Searched refs:ResultReg2 (Results 1 – 4 of 4) sorted by relevance
3646 unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0; in fastLowerIntrinsicCall() local3741 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass, in fastLowerIntrinsicCall()3744 (void)ResultReg2; in fastLowerIntrinsicCall()3745 assert((ResultReg1 + 1) == ResultReg2 && in fastLowerIntrinsicCall()5035 const unsigned ResultReg2 = createResultReg(&AArch64::GPR32RegClass); in selectAtomicCmpXchg() local5053 .addDef(ResultReg2) in selectAtomicCmpXchg()5058 assert((ResultReg1 + 1) == ResultReg2 && "Nonconsecutive result registers."); in selectAtomicCmpXchg()
3560 unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0; in fastLowerIntrinsicCall() local3655 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass, in fastLowerIntrinsicCall()3658 (void)ResultReg2; in fastLowerIntrinsicCall()3659 assert((ResultReg1 + 1) == ResultReg2 && in fastLowerIntrinsicCall()
2813 unsigned ResultReg2 = FuncInfo.CreateRegs(CondTy); in fastLowerIntrinsicCall() local2814 assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers."); in fastLowerIntrinsicCall()2816 ResultReg2); in fastLowerIntrinsicCall()
2997 unsigned ResultReg2 = createResultReg(&X86::GR8RegClass); in fastLowerIntrinsicCall() local2998 assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers."); in fastLowerIntrinsicCall()3000 ResultReg2); in fastLowerIntrinsicCall()