| /external/v8/src/compiler/ |
| D | machine-operator.h | 709 V(Word, Ror) \ in NON_EXPORTED_BASE()
|
| /external/v8/src/wasm/ |
| D | wasm-opcodes.cc | 97 CASE_INT_OP(Ror, "ror") in OpcodeName()
|
| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 3539 COMPARE_T32(Ror(eq, r7, r7, r3), in TEST()
3543 COMPARE_T32(Ror(eq, r8, r8, r3), in TEST()
3547 COMPARE_T32(Ror(eq, r0, r1, 16), in TEST()
4166 CHECK_T32_16(Ror(DontCare, r0, r0, r1), "rors r0, r1\n"); in TEST()
4168 CHECK_T32_16_IT_BLOCK(Ror(DontCare, eq, r0, r0, r1), in TEST()
|
| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 148 M(Ror) \
|
| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 148 M(Ror) \
|
| D | test-assembler-aarch32.cc | 786 __ Ror(r6, r1, 20); in TEST() local
816 __ Ror(r6, r1, r9); in TEST() local
|
| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.h | 1066 void Ror(Register rd, Register rm, const Operand& shift_imm,
1068 void Ror(Register rd, Register rm, Register rs, Condition cond = AL);
|
| D | assembler_arm.cc | 2662 void Assembler::Ror(Register rd, Register rm, const Operand& shift_imm, in Ror() function in dart::Assembler
2670 void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) { in Ror() function in dart::Assembler
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 853 void TurboAssembler::Ror(const Register& rd, const Register& rs, in Ror() function
860 void TurboAssembler::Ror(const Register& rd, const Register& rn, in Ror() function
|
| D | macro-assembler-arm64.h | 923 inline void Ror(const Register& rd, const Register& rs, unsigned shift);
924 inline void Ror(const Register& rd, const Register& rn, const Register& rm);
|
| /external/honggfuzz/examples/apache-httpd/corpus_http2/ |
| D | 1109e34c5bbd66e62167e3986a0f7ace.0000b27c.honggfuzz.cov | 239 …�0}y��� ��F'ء21¿�λ�COſ���M%�uS��<'��UZP�� �b#��f{�t~�CtlJ�_�6*N�VD<p�1Ror������ɔ�?�+��'A�/…
264 …�0}y��� ��F'ء21¿�λ�COſ���M%�uS��<'��UZP�� �b#��f{�t~�CtlJ�_�6*N�VD<p�1Ror������ɔ�?�+��'A�/…
|
| D | 11eed1760d4ac87ca521bab29af44a5b.000127c6.honggfuzz.cov | 258 …D��ؙ�!�p�'�A G�f*1ni��'�O1Y6�M�w�̾�j�諘*�8������� ĥ�� �'IqPy6��F1�-��G���Ror�Ș7���ߢ� �A�����~`s…
390 …D��ؙ�!�p�'�A G�f*1ni��'�O1Y6�M�w�̾�j�諘*�8������� ĥ�� �'IqPy6��F1�-��G���Ror�Ș7���ߢ� �A�����~`s…
500 …D��ؙ�!�p�'�A G�f*1ni��'�O1Y6�M�w�̾�j�諘*�8������� ĥ�� �'IqPy6��F1�-��G���Ror�Ș7���ߢ� �A�����~`s…
|
| D | 4dd04d0b031431f67d5aff8d2da2a66b.0001aa43.honggfuzz.cov | 346 …�0}y��� ��F'ء21¿�λ�COſ���M%�uS��<'��UZP�� �b#��f{�t~�CtlJ�_�6*N�VD<p�1Ror������ɔ�?�+��'A�/…
|
| /external/honggfuzz/examples/apache-httpd/corpus_http1/ |
| D | 1109e34c5bbd66e62167e3986a0f7ace.0000b27c.honggfuzz.cov | 239 …�0}y��� ��F'ء21¿�λ�COſ���M%�uS��<'��UZP�� �b#��f{�t~�CtlJ�_�6*N�VD<p�1Ror������ɔ�?�+��'A�/…
264 …�0}y��� ��F'ء21¿�λ�COſ���M%�uS��<'��UZP�� �b#��f{�t~�CtlJ�_�6*N�VD<p�1Ror������ɔ�?�+��'A�/…
|
| D | 11eed1760d4ac87ca521bab29af44a5b.000127c6.honggfuzz.cov | 258 …D��ؙ�!�p�'�A G�f*1ni��'�O1Y6�M�w�̾�j�諘*�8������� ĥ�� �'IqPy6��F1�-��G���Ror�Ș7���ߢ� �A�����~`s…
390 …D��ؙ�!�p�'�A G�f*1ni��'�O1Y6�M�w�̾�j�諘*�8������� ĥ�� �'IqPy6��F1�-��G���Ror�Ș7���ߢ� �A�����~`s…
500 …D��ؙ�!�p�'�A G�f*1ni��'�O1Y6�M�w�̾�j�諘*�8������� ĥ�� �'IqPy6��F1�-��G���Ror�Ș7���ߢ� �A�����~`s…
|
| D | 25bc7423f93338ec013a6c15f688f37a.0000fedc.honggfuzz.cov | 345 …�0}y��� ��F'ء21¿�λ�COſ���M%�uS��<'��UZP�� �b#��f{�t~�CtlJ�_�6*N�VD<p�1Ror������ɔ�?�+��'A�/…
|
| /external/v8/src/mips/ |
| D | macro-assembler-mips.h | 461 DEFINE_INSTRUCTION(Ror);
|
| D | macro-assembler-mips.cc | 906 void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) { in Ror() function in v8::internal::TurboAssembler
1700 Ror(dest, dest, pos); in InsertBits()
1707 Ror(dest, dest, scratch); in InsertBits()
2564 Ror(rd, rs, 16); in Ctz()
|
| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.h | 472 DEFINE_INSTRUCTION(Ror);
|
| D | macro-assembler-mips64.cc | 1044 void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) { in Ror() function in v8::internal::TurboAssembler
2063 Ror(dest, dest, pos); in InsertBits()
2070 Ror(dest, dest, scratch); in InsertBits()
|
| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1158 ASSEMBLE_SHIFT(Ror, 64); in AssembleArchInstruction()
1161 ASSEMBLE_SHIFT(Ror, 32); in AssembleArchInstruction()
|
| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 10208 __ Ror(x16, x0, x1); in TEST() local
10209 __ Ror(x17, x0, x2); in TEST() local
10210 __ Ror(x18, x0, x3); in TEST() local
10211 __ Ror(x19, x0, x4); in TEST() local
10212 __ Ror(x20, x0, x5); in TEST() local
10213 __ Ror(x21, x0, x6); in TEST() local
10215 __ Ror(w22, w0, w1); in TEST() local
10216 __ Ror(w23, w0, w2); in TEST() local
10217 __ Ror(w24, w0, w3); in TEST() local
10218 __ Ror(w25, w0, w4); in TEST() local
[all …]
|
| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 3095 void Ror(Condition cond, Register rd, Register rm, const Operand& operand) { in Ror() function
3109 void Ror(Register rd, Register rm, const Operand& operand) { in Ror() function
3110 Ror(al, rd, rm, operand); in Ror()
3112 void Ror(FlagsUpdate flags, in Ror() function
3119 Ror(cond, rd, rm, operand); in Ror()
3131 Ror(cond, rd, rm, operand); in Ror()
3136 void Ror(FlagsUpdate flags, in Ror() function
3140 Ror(flags, al, rd, rm, operand); in Ror()
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 2121 void Ror(const Register& rd, const Register& rs, unsigned shift) { in Ror() function
2128 void Ror(const Register& rd, const Register& rn, const Register& rm) { in Ror() function
|
| /external/v8/src/compiler/mips/ |
| D | code-generator-mips.cc | 1093 __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); in AssembleArchInstruction() local
|