| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | atomic-minmax.ll | 235 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
238 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
262 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
265 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
289 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
292 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
314 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
317 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
339 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
342 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 143 def SA1 : Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>;
168 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
259 (add LC0, SA0, LC1, SA1,
273 LC0, LC1, SA0, SA1, USR, USR_OVF, CS0, CS1,
|
| D | HexagonRegisterInfo.cpp | 148 Reserved.set(Hexagon::SA1); in getReservedRegs()
|
| D | HexagonHardwareLoops.cpp | 964 R == Hexagon::LC1 || R == Hexagon::SA1)) in isInvalidLoopOperation()
966 if (!IsInnerHWLoop && (R == Hexagon::LC1 || R == Hexagon::SA1)) in isInvalidLoopOperation()
|
| D | HexagonInstrInfo.td | 4563 let Defs = [SA1, LC1] in
4574 Defs = [PC, LC1], Uses = [SA1, LC1] in {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | mmx-coalescing.ll | 23 %SA1 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 3
24 %v2 = load i8*, i8** %SA1, align 8
|
| /external/llvm/test/CodeGen/X86/ |
| D | mmx-coalescing.ll | 23 %SA1 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 3
24 %v2 = load i8*, i8** %SA1, align 8
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.h | 107 return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R || in isLoopRegister()
|
| D | HexagonMCChecker.cpp | 50 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
|
| /external/ipsec-tools/src/racoon/ |
| D | TODO | 50 +--------------SA1----------------+
64 +--------------SA1----------------+
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.h | 189 Hexagon::SA1 == R || Hexagon::LC1 == R); in isLoopRegister()
|
| D | HexagonMCChecker.cpp | 43 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 136 def SA1: Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>;
168 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
348 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
|
| D | HexagonPseudo.td | 99 Defs = [PC, LC1], Uses = [SA1, LC1] in {
106 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
157 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
|
| D | HexagonRegisterInfo.cpp | 159 Reserved.set(Hexagon::SA1); // C2 in getReservedRegs()
|
| D | HexagonHardwareLoops.cpp | 999 static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 }; in isInvalidLoopOperation()
1000 static const unsigned Regs1[] = { LC1, SA1 }; in isInvalidLoopOperation()
|
| D | HexagonDepInstrInfo.td | 4879 let Uses = [LC0, LC1, SA0, SA1];
4888 let Uses = [LC1, SA1];
5514 let Defs = [LC1, SA1];
5532 let Defs = [LC1, SA1];
|
| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/Analysis/ |
| D | MemorySSA.cpp | 1054 StoreInst *SA1 = B.CreateStore(ConstantInt::get(Int8, 1), AllocaA); in TEST_F() local
1066 for (StoreInst *V : {SA1, SB1, SA2, SB2, SA3, SB3}) { in TEST_F()
1073 if (V == SA1) in TEST_F()
1150 StoreInst *SA1 = B.CreateStore(ConstantInt::get(Int8, 0), PointerA); in TEST_F() local
1163 std::initializer_list<StoreInst *> Sts = {SA1, SB1, SC1, SA2, SB2, SC2, SB3}; in TEST_F()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 691 /* 0 */ SA0, LC0, SA1, LC1, in DecodeCtrRegsRegisterClass()
|
| /external/ImageMagick/PerlMagick/t/reference/write/filter/ |
| D | Solarize.miff | 44 …80�>83�=71�>94�@=9�IA6�P@-�H?-�K81�C74�5=0�@?/�YI@�P4+�[4!�YA&�V:$�_6'�V=2�SA1�O@2�@@4�38)�1+�++…
|
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 565 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, in DecodeCtrRegsRegisterClass()
|
| /external/honggfuzz/examples/apache-httpd/corpus_http2/ |
| D | 551d0e35c026a1478e07a930e12bd18f.0008bfad.honggfuzz.cov | 595 ��s��I.�SA1�Zs���k�� �˒�m�!Zq�b&��F�U�Xn4��K5��9 ����:=A1�_� pe� :�L�
|