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Searched refs:SCG_PLL_CFG_PLLSEL_MASK (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-mx7ulp/
Dscg.h185 #define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT) macro
/external/u-boot/arch/arm/mach-imx/mx7ulp/
Dscg.c271 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; in scg_apll_get_rate()
299 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; in scg_spll_get_rate()