1 /* 2 * Copyright © 2017 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27 #if !defined (_vega10_ENUM_HEADER) 28 #define _vega10_ENUM_HEADER 29 30 31 #ifndef _DRIVER_BUILD 32 #ifndef GL_ZERO 33 #define GL__ZERO BLEND_ZERO 34 #define GL__ONE BLEND_ONE 35 #define GL__SRC_COLOR BLEND_SRC_COLOR 36 #define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR 37 #define GL__DST_COLOR BLEND_DST_COLOR 38 #define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR 39 #define GL__SRC_ALPHA BLEND_SRC_ALPHA 40 #define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA 41 #define GL__DST_ALPHA BLEND_DST_ALPHA 42 #define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA 43 #define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE 44 #define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR 45 #define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR 46 #define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA 47 #define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA 48 #endif 49 #endif 50 51 /******************************************************* 52 * GDS DATA_TYPE Enums 53 *******************************************************/ 54 55 #ifndef ENUMS_GDS_PERFCOUNT_SELECT_H 56 #define ENUMS_GDS_PERFCOUNT_SELECT_H 57 typedef enum GDS_PERFCOUNT_SELECT { 58 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 59 GDS_PERF_SEL_DS_BANK_CONFL = 1, 60 GDS_PERF_SEL_WBUF_FLUSH = 2, 61 GDS_PERF_SEL_WR_COMP = 3, 62 GDS_PERF_SEL_WBUF_WR = 4, 63 GDS_PERF_SEL_RBUF_HIT = 5, 64 GDS_PERF_SEL_RBUF_MISS = 6, 65 GDS_PERF_SEL_SE0_SH0_NORET = 7, 66 GDS_PERF_SEL_SE0_SH0_RET = 8, 67 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9, 68 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10, 69 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11, 70 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12, 71 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13, 72 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14, 73 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15, 74 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16, 75 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17, 76 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18, 77 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19, 78 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20, 79 GDS_PERF_SEL_SE0_SH1_NORET = 21, 80 GDS_PERF_SEL_SE0_SH1_RET = 22, 81 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23, 82 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24, 83 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25, 84 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26, 85 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27, 86 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28, 87 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29, 88 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30, 89 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31, 90 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32, 91 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33, 92 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34, 93 GDS_PERF_SEL_SE1_SH0_NORET = 35, 94 GDS_PERF_SEL_SE1_SH0_RET = 36, 95 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37, 96 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38, 97 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39, 98 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40, 99 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41, 100 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42, 101 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43, 102 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44, 103 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45, 104 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46, 105 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47, 106 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48, 107 GDS_PERF_SEL_SE1_SH1_NORET = 49, 108 GDS_PERF_SEL_SE1_SH1_RET = 50, 109 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51, 110 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52, 111 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53, 112 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54, 113 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55, 114 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56, 115 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57, 116 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58, 117 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59, 118 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60, 119 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61, 120 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62, 121 GDS_PERF_SEL_SE2_SH0_NORET = 63, 122 GDS_PERF_SEL_SE2_SH0_RET = 64, 123 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65, 124 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66, 125 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67, 126 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68, 127 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69, 128 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70, 129 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71, 130 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72, 131 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73, 132 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74, 133 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75, 134 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76, 135 GDS_PERF_SEL_SE2_SH1_NORET = 77, 136 GDS_PERF_SEL_SE2_SH1_RET = 78, 137 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79, 138 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80, 139 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81, 140 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82, 141 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83, 142 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84, 143 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85, 144 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86, 145 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87, 146 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88, 147 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89, 148 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90, 149 GDS_PERF_SEL_SE3_SH0_NORET = 91, 150 GDS_PERF_SEL_SE3_SH0_RET = 92, 151 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93, 152 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94, 153 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95, 154 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96, 155 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97, 156 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98, 157 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99, 158 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100, 159 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101, 160 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102, 161 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103, 162 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104, 163 GDS_PERF_SEL_SE3_SH1_NORET = 105, 164 GDS_PERF_SEL_SE3_SH1_RET = 106, 165 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107, 166 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108, 167 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109, 168 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110, 169 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111, 170 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112, 171 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113, 172 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114, 173 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115, 174 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116, 175 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117, 176 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118, 177 GDS_PERF_SEL_GWS_RELEASED = 119, 178 GDS_PERF_SEL_GWS_BYPASS = 120, 179 } GDS_PERFCOUNT_SELECT; 180 #endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/ 181 182 /******************************************************* 183 * Chip Enums 184 *******************************************************/ 185 186 /* 187 * SurfaceEndian enum 188 */ 189 190 typedef enum SurfaceEndian { 191 ENDIAN_NONE = 0x00000000, 192 ENDIAN_8IN16 = 0x00000001, 193 ENDIAN_8IN32 = 0x00000002, 194 ENDIAN_8IN64 = 0x00000003, 195 } SurfaceEndian; 196 197 /* 198 * ArrayMode enum 199 */ 200 201 typedef enum ArrayMode { 202 ARRAY_LINEAR_GENERAL = 0x00000000, 203 ARRAY_LINEAR_ALIGNED = 0x00000001, 204 ARRAY_1D_TILED_THIN1 = 0x00000002, 205 ARRAY_1D_TILED_THICK = 0x00000003, 206 ARRAY_2D_TILED_THIN1 = 0x00000004, 207 ARRAY_PRT_TILED_THIN1 = 0x00000005, 208 ARRAY_PRT_2D_TILED_THIN1 = 0x00000006, 209 ARRAY_2D_TILED_THICK = 0x00000007, 210 ARRAY_2D_TILED_XTHICK = 0x00000008, 211 ARRAY_PRT_TILED_THICK = 0x00000009, 212 ARRAY_PRT_2D_TILED_THICK = 0x0000000a, 213 ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b, 214 ARRAY_3D_TILED_THIN1 = 0x0000000c, 215 ARRAY_3D_TILED_THICK = 0x0000000d, 216 ARRAY_3D_TILED_XTHICK = 0x0000000e, 217 ARRAY_PRT_3D_TILED_THICK = 0x0000000f, 218 } ArrayMode; 219 220 /* 221 * PipeTiling enum 222 */ 223 224 typedef enum PipeTiling { 225 CONFIG_1_PIPE = 0x00000000, 226 CONFIG_2_PIPE = 0x00000001, 227 CONFIG_4_PIPE = 0x00000002, 228 CONFIG_8_PIPE = 0x00000003, 229 } PipeTiling; 230 231 /* 232 * BankTiling enum 233 */ 234 235 typedef enum BankTiling { 236 CONFIG_4_BANK = 0x00000000, 237 CONFIG_8_BANK = 0x00000001, 238 } BankTiling; 239 240 /* 241 * GroupInterleave enum 242 */ 243 244 typedef enum GroupInterleave { 245 CONFIG_256B_GROUP = 0x00000000, 246 CONFIG_512B_GROUP = 0x00000001, 247 } GroupInterleave; 248 249 /* 250 * RowTiling enum 251 */ 252 253 typedef enum RowTiling { 254 CONFIG_1KB_ROW = 0x00000000, 255 CONFIG_2KB_ROW = 0x00000001, 256 CONFIG_4KB_ROW = 0x00000002, 257 CONFIG_8KB_ROW = 0x00000003, 258 CONFIG_1KB_ROW_OPT = 0x00000004, 259 CONFIG_2KB_ROW_OPT = 0x00000005, 260 CONFIG_4KB_ROW_OPT = 0x00000006, 261 CONFIG_8KB_ROW_OPT = 0x00000007, 262 } RowTiling; 263 264 /* 265 * BankSwapBytes enum 266 */ 267 268 typedef enum BankSwapBytes { 269 CONFIG_128B_SWAPS = 0x00000000, 270 CONFIG_256B_SWAPS = 0x00000001, 271 CONFIG_512B_SWAPS = 0x00000002, 272 CONFIG_1KB_SWAPS = 0x00000003, 273 } BankSwapBytes; 274 275 /* 276 * SampleSplitBytes enum 277 */ 278 279 typedef enum SampleSplitBytes { 280 CONFIG_1KB_SPLIT = 0x00000000, 281 CONFIG_2KB_SPLIT = 0x00000001, 282 CONFIG_4KB_SPLIT = 0x00000002, 283 CONFIG_8KB_SPLIT = 0x00000003, 284 } SampleSplitBytes; 285 286 /* 287 * NumPipes enum 288 */ 289 290 typedef enum NumPipes { 291 ADDR_CONFIG_1_PIPE = 0x00000000, 292 ADDR_CONFIG_2_PIPE = 0x00000001, 293 ADDR_CONFIG_4_PIPE = 0x00000002, 294 ADDR_CONFIG_8_PIPE = 0x00000003, 295 ADDR_CONFIG_16_PIPE = 0x00000004, 296 ADDR_CONFIG_32_PIPE = 0x00000005, 297 } NumPipes; 298 299 /* 300 * NumBanksConfig enum 301 */ 302 303 typedef enum NumBanksConfig { 304 ADDR_CONFIG_1_BANK = 0x00000000, 305 ADDR_CONFIG_2_BANK = 0x00000001, 306 ADDR_CONFIG_4_BANK = 0x00000002, 307 ADDR_CONFIG_8_BANK = 0x00000003, 308 ADDR_CONFIG_16_BANK = 0x00000004, 309 } NumBanksConfig; 310 311 /* 312 * PipeInterleaveSize enum 313 */ 314 315 typedef enum PipeInterleaveSize { 316 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, 317 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, 318 ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, 319 ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, 320 } PipeInterleaveSize; 321 322 /* 323 * BankInterleaveSize enum 324 */ 325 326 typedef enum BankInterleaveSize { 327 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, 328 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, 329 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, 330 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, 331 } BankInterleaveSize; 332 333 /* 334 * NumShaderEngines enum 335 */ 336 337 typedef enum NumShaderEngines { 338 ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, 339 ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, 340 ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, 341 ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, 342 } NumShaderEngines; 343 344 /* 345 * NumRbPerShaderEngine enum 346 */ 347 348 typedef enum NumRbPerShaderEngine { 349 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, 350 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, 351 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, 352 } NumRbPerShaderEngine; 353 354 /* 355 * NumGPUs enum 356 */ 357 358 typedef enum NumGPUs { 359 ADDR_CONFIG_1_GPU = 0x00000000, 360 ADDR_CONFIG_2_GPU = 0x00000001, 361 ADDR_CONFIG_4_GPU = 0x00000002, 362 ADDR_CONFIG_8_GPU = 0x00000003, 363 } NumGPUs; 364 365 /* 366 * NumMaxCompressedFragments enum 367 */ 368 369 typedef enum NumMaxCompressedFragments { 370 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, 371 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, 372 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, 373 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, 374 } NumMaxCompressedFragments; 375 376 /* 377 * ShaderEngineTileSize enum 378 */ 379 380 typedef enum ShaderEngineTileSize { 381 ADDR_CONFIG_SE_TILE_16 = 0x00000000, 382 ADDR_CONFIG_SE_TILE_32 = 0x00000001, 383 } ShaderEngineTileSize; 384 385 /* 386 * MultiGPUTileSize enum 387 */ 388 389 typedef enum MultiGPUTileSize { 390 ADDR_CONFIG_GPU_TILE_16 = 0x00000000, 391 ADDR_CONFIG_GPU_TILE_32 = 0x00000001, 392 ADDR_CONFIG_GPU_TILE_64 = 0x00000002, 393 ADDR_CONFIG_GPU_TILE_128 = 0x00000003, 394 } MultiGPUTileSize; 395 396 /* 397 * RowSize enum 398 */ 399 400 typedef enum RowSize { 401 ADDR_CONFIG_1KB_ROW = 0x00000000, 402 ADDR_CONFIG_2KB_ROW = 0x00000001, 403 ADDR_CONFIG_4KB_ROW = 0x00000002, 404 } RowSize; 405 406 /* 407 * NumLowerPipes enum 408 */ 409 410 typedef enum NumLowerPipes { 411 ADDR_CONFIG_1_LOWER_PIPES = 0x00000000, 412 ADDR_CONFIG_2_LOWER_PIPES = 0x00000001, 413 } NumLowerPipes; 414 415 /* 416 * ColorTransform enum 417 */ 418 419 typedef enum ColorTransform { 420 DCC_CT_AUTO = 0x00000000, 421 DCC_CT_NONE = 0x00000001, 422 ABGR_TO_A_BG_G_RB = 0x00000002, 423 BGRA_TO_BG_G_RB_A = 0x00000003, 424 } ColorTransform; 425 426 /* 427 * CompareRef enum 428 */ 429 430 typedef enum CompareRef { 431 REF_NEVER = 0x00000000, 432 REF_LESS = 0x00000001, 433 REF_EQUAL = 0x00000002, 434 REF_LEQUAL = 0x00000003, 435 REF_GREATER = 0x00000004, 436 REF_NOTEQUAL = 0x00000005, 437 REF_GEQUAL = 0x00000006, 438 REF_ALWAYS = 0x00000007, 439 } CompareRef; 440 441 /* 442 * ReadSize enum 443 */ 444 445 typedef enum ReadSize { 446 READ_256_BITS = 0x00000000, 447 READ_512_BITS = 0x00000001, 448 } ReadSize; 449 450 /* 451 * DepthFormat enum 452 */ 453 454 typedef enum DepthFormat { 455 DEPTH_INVALID = 0x00000000, 456 DEPTH_16 = 0x00000001, 457 DEPTH_X8_24 = 0x00000002, 458 DEPTH_8_24 = 0x00000003, 459 DEPTH_X8_24_FLOAT = 0x00000004, 460 DEPTH_8_24_FLOAT = 0x00000005, 461 DEPTH_32_FLOAT = 0x00000006, 462 DEPTH_X24_8_32_FLOAT = 0x00000007, 463 } DepthFormat; 464 465 /* 466 * ZFormat enum 467 */ 468 469 typedef enum ZFormat { 470 Z_INVALID = 0x00000000, 471 Z_16 = 0x00000001, 472 Z_24 = 0x00000002, 473 Z_32_FLOAT = 0x00000003, 474 } ZFormat; 475 476 /* 477 * StencilFormat enum 478 */ 479 480 typedef enum StencilFormat { 481 STENCIL_INVALID = 0x00000000, 482 STENCIL_8 = 0x00000001, 483 } StencilFormat; 484 485 /* 486 * CmaskMode enum 487 */ 488 489 typedef enum CmaskMode { 490 CMASK_CLEAR_NONE = 0x00000000, 491 CMASK_CLEAR_ONE = 0x00000001, 492 CMASK_CLEAR_ALL = 0x00000002, 493 CMASK_ANY_EXPANDED = 0x00000003, 494 CMASK_ALPHA0_FRAG1 = 0x00000004, 495 CMASK_ALPHA0_FRAG2 = 0x00000005, 496 CMASK_ALPHA0_FRAG4 = 0x00000006, 497 CMASK_ALPHA0_FRAGS = 0x00000007, 498 CMASK_ALPHA1_FRAG1 = 0x00000008, 499 CMASK_ALPHA1_FRAG2 = 0x00000009, 500 CMASK_ALPHA1_FRAG4 = 0x0000000a, 501 CMASK_ALPHA1_FRAGS = 0x0000000b, 502 CMASK_ALPHAX_FRAG1 = 0x0000000c, 503 CMASK_ALPHAX_FRAG2 = 0x0000000d, 504 CMASK_ALPHAX_FRAG4 = 0x0000000e, 505 CMASK_ALPHAX_FRAGS = 0x0000000f, 506 } CmaskMode; 507 508 /* 509 * QuadExportFormat enum 510 */ 511 512 typedef enum QuadExportFormat { 513 EXPORT_UNUSED = 0x00000000, 514 EXPORT_32_R = 0x00000001, 515 EXPORT_32_GR = 0x00000002, 516 EXPORT_32_AR = 0x00000003, 517 EXPORT_FP16_ABGR = 0x00000004, 518 EXPORT_UNSIGNED16_ABGR = 0x00000005, 519 EXPORT_SIGNED16_ABGR = 0x00000006, 520 EXPORT_32_ABGR = 0x00000007, 521 EXPORT_32BPP_8PIX = 0x00000008, 522 EXPORT_16_16_UNSIGNED_8PIX = 0x00000009, 523 EXPORT_16_16_SIGNED_8PIX = 0x0000000a, 524 EXPORT_16_16_FLOAT_8PIX = 0x0000000b, 525 } QuadExportFormat; 526 527 /* 528 * QuadExportFormatOld enum 529 */ 530 531 typedef enum QuadExportFormatOld { 532 EXPORT_4P_32BPC_ABGR = 0x00000000, 533 EXPORT_4P_16BPC_ABGR = 0x00000001, 534 EXPORT_4P_32BPC_GR = 0x00000002, 535 EXPORT_4P_32BPC_AR = 0x00000003, 536 EXPORT_2P_32BPC_ABGR = 0x00000004, 537 EXPORT_8P_32BPC_R = 0x00000005, 538 } QuadExportFormatOld; 539 540 /* 541 * ColorFormat enum 542 */ 543 544 typedef enum ColorFormat { 545 COLOR_INVALID = 0x00000000, 546 COLOR_8 = 0x00000001, 547 COLOR_16 = 0x00000002, 548 COLOR_8_8 = 0x00000003, 549 COLOR_32 = 0x00000004, 550 COLOR_16_16 = 0x00000005, 551 COLOR_10_11_11 = 0x00000006, 552 COLOR_11_11_10 = 0x00000007, 553 COLOR_10_10_10_2 = 0x00000008, 554 COLOR_2_10_10_10 = 0x00000009, 555 COLOR_8_8_8_8 = 0x0000000a, 556 COLOR_32_32 = 0x0000000b, 557 COLOR_16_16_16_16 = 0x0000000c, 558 COLOR_RESERVED_13 = 0x0000000d, 559 COLOR_32_32_32_32 = 0x0000000e, 560 COLOR_RESERVED_15 = 0x0000000f, 561 COLOR_5_6_5 = 0x00000010, 562 COLOR_1_5_5_5 = 0x00000011, 563 COLOR_5_5_5_1 = 0x00000012, 564 COLOR_4_4_4_4 = 0x00000013, 565 COLOR_8_24 = 0x00000014, 566 COLOR_24_8 = 0x00000015, 567 COLOR_X24_8_32_FLOAT = 0x00000016, 568 COLOR_RESERVED_23 = 0x00000017, 569 COLOR_RESERVED_24 = 0x00000018, 570 COLOR_RESERVED_25 = 0x00000019, 571 COLOR_RESERVED_26 = 0x0000001a, 572 COLOR_RESERVED_27 = 0x0000001b, 573 COLOR_RESERVED_28 = 0x0000001c, 574 COLOR_RESERVED_29 = 0x0000001d, 575 COLOR_RESERVED_30 = 0x0000001e, 576 COLOR_2_10_10_10_6E4 = 0x0000001f, 577 } ColorFormat; 578 579 /* 580 * SurfaceFormat enum 581 */ 582 583 typedef enum SurfaceFormat { 584 FMT_INVALID = 0x00000000, 585 FMT_8 = 0x00000001, 586 FMT_16 = 0x00000002, 587 FMT_8_8 = 0x00000003, 588 FMT_32 = 0x00000004, 589 FMT_16_16 = 0x00000005, 590 FMT_10_11_11 = 0x00000006, 591 FMT_11_11_10 = 0x00000007, 592 FMT_10_10_10_2 = 0x00000008, 593 FMT_2_10_10_10 = 0x00000009, 594 FMT_8_8_8_8 = 0x0000000a, 595 FMT_32_32 = 0x0000000b, 596 FMT_16_16_16_16 = 0x0000000c, 597 FMT_32_32_32 = 0x0000000d, 598 FMT_32_32_32_32 = 0x0000000e, 599 FMT_RESERVED_4 = 0x0000000f, 600 FMT_5_6_5 = 0x00000010, 601 FMT_1_5_5_5 = 0x00000011, 602 FMT_5_5_5_1 = 0x00000012, 603 FMT_4_4_4_4 = 0x00000013, 604 FMT_8_24 = 0x00000014, 605 FMT_24_8 = 0x00000015, 606 FMT_X24_8_32_FLOAT = 0x00000016, 607 FMT_RESERVED_33 = 0x00000017, 608 FMT_11_11_10_FLOAT = 0x00000018, 609 FMT_16_FLOAT = 0x00000019, 610 FMT_32_FLOAT = 0x0000001a, 611 FMT_16_16_FLOAT = 0x0000001b, 612 FMT_8_24_FLOAT = 0x0000001c, 613 FMT_24_8_FLOAT = 0x0000001d, 614 FMT_32_32_FLOAT = 0x0000001e, 615 FMT_10_11_11_FLOAT = 0x0000001f, 616 FMT_16_16_16_16_FLOAT = 0x00000020, 617 FMT_3_3_2 = 0x00000021, 618 FMT_6_5_5 = 0x00000022, 619 FMT_32_32_32_32_FLOAT = 0x00000023, 620 FMT_RESERVED_36 = 0x00000024, 621 FMT_1 = 0x00000025, 622 FMT_1_REVERSED = 0x00000026, 623 FMT_GB_GR = 0x00000027, 624 FMT_BG_RG = 0x00000028, 625 FMT_32_AS_8 = 0x00000029, 626 FMT_32_AS_8_8 = 0x0000002a, 627 FMT_5_9_9_9_SHAREDEXP = 0x0000002b, 628 FMT_8_8_8 = 0x0000002c, 629 FMT_16_16_16 = 0x0000002d, 630 FMT_16_16_16_FLOAT = 0x0000002e, 631 FMT_4_4 = 0x0000002f, 632 FMT_32_32_32_FLOAT = 0x00000030, 633 FMT_BC1 = 0x00000031, 634 FMT_BC2 = 0x00000032, 635 FMT_BC3 = 0x00000033, 636 FMT_BC4 = 0x00000034, 637 FMT_BC5 = 0x00000035, 638 FMT_BC6 = 0x00000036, 639 FMT_BC7 = 0x00000037, 640 FMT_32_AS_32_32_32_32 = 0x00000038, 641 FMT_APC3 = 0x00000039, 642 FMT_APC4 = 0x0000003a, 643 FMT_APC5 = 0x0000003b, 644 FMT_APC6 = 0x0000003c, 645 FMT_APC7 = 0x0000003d, 646 FMT_CTX1 = 0x0000003e, 647 FMT_RESERVED_63 = 0x0000003f, 648 } SurfaceFormat; 649 650 /* 651 * BUF_DATA_FORMAT enum 652 */ 653 654 typedef enum BUF_DATA_FORMAT { 655 BUF_DATA_FORMAT_INVALID = 0x00000000, 656 BUF_DATA_FORMAT_8 = 0x00000001, 657 BUF_DATA_FORMAT_16 = 0x00000002, 658 BUF_DATA_FORMAT_8_8 = 0x00000003, 659 BUF_DATA_FORMAT_32 = 0x00000004, 660 BUF_DATA_FORMAT_16_16 = 0x00000005, 661 BUF_DATA_FORMAT_10_11_11 = 0x00000006, 662 BUF_DATA_FORMAT_11_11_10 = 0x00000007, 663 BUF_DATA_FORMAT_10_10_10_2 = 0x00000008, 664 BUF_DATA_FORMAT_2_10_10_10 = 0x00000009, 665 BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a, 666 BUF_DATA_FORMAT_32_32 = 0x0000000b, 667 BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c, 668 BUF_DATA_FORMAT_32_32_32 = 0x0000000d, 669 BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e, 670 BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f, 671 } BUF_DATA_FORMAT; 672 673 /* 674 * IMG_DATA_FORMAT enum 675 */ 676 677 typedef enum IMG_DATA_FORMAT { 678 IMG_DATA_FORMAT_INVALID = 0x00000000, 679 IMG_DATA_FORMAT_8 = 0x00000001, 680 IMG_DATA_FORMAT_16 = 0x00000002, 681 IMG_DATA_FORMAT_8_8 = 0x00000003, 682 IMG_DATA_FORMAT_32 = 0x00000004, 683 IMG_DATA_FORMAT_16_16 = 0x00000005, 684 IMG_DATA_FORMAT_10_11_11 = 0x00000006, 685 IMG_DATA_FORMAT_11_11_10 = 0x00000007, 686 IMG_DATA_FORMAT_10_10_10_2 = 0x00000008, 687 IMG_DATA_FORMAT_2_10_10_10 = 0x00000009, 688 IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a, 689 IMG_DATA_FORMAT_32_32 = 0x0000000b, 690 IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c, 691 IMG_DATA_FORMAT_32_32_32 = 0x0000000d, 692 IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e, 693 IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f, 694 IMG_DATA_FORMAT_5_6_5 = 0x00000010, 695 IMG_DATA_FORMAT_1_5_5_5 = 0x00000011, 696 IMG_DATA_FORMAT_5_5_5_1 = 0x00000012, 697 IMG_DATA_FORMAT_4_4_4_4 = 0x00000013, 698 IMG_DATA_FORMAT_8_24 = 0x00000014, 699 IMG_DATA_FORMAT_24_8 = 0x00000015, 700 IMG_DATA_FORMAT_X24_8_32 = 0x00000016, 701 IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x00000017, 702 IMG_DATA_FORMAT_ETC2_RGB = 0x00000018, 703 IMG_DATA_FORMAT_ETC2_RGBA = 0x00000019, 704 IMG_DATA_FORMAT_ETC2_R = 0x0000001a, 705 IMG_DATA_FORMAT_ETC2_RG = 0x0000001b, 706 IMG_DATA_FORMAT_ETC2_RGBA1 = 0x0000001c, 707 IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d, 708 IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e, 709 IMG_DATA_FORMAT_6E4 = 0x0000001f, 710 IMG_DATA_FORMAT_GB_GR = 0x00000020, 711 IMG_DATA_FORMAT_BG_RG = 0x00000021, 712 IMG_DATA_FORMAT_5_9_9_9 = 0x00000022, 713 IMG_DATA_FORMAT_BC1 = 0x00000023, 714 IMG_DATA_FORMAT_BC2 = 0x00000024, 715 IMG_DATA_FORMAT_BC3 = 0x00000025, 716 IMG_DATA_FORMAT_BC4 = 0x00000026, 717 IMG_DATA_FORMAT_BC5 = 0x00000027, 718 IMG_DATA_FORMAT_BC6 = 0x00000028, 719 IMG_DATA_FORMAT_BC7 = 0x00000029, 720 IMG_DATA_FORMAT_16_AS_32_32 = 0x0000002a, 721 IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x0000002b, 722 IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x0000002c, 723 IMG_DATA_FORMAT_FMASK = 0x0000002d, 724 IMG_DATA_FORMAT_ASTC_2D_LDR = 0x0000002e, 725 IMG_DATA_FORMAT_ASTC_2D_HDR = 0x0000002f, 726 IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 0x00000030, 727 IMG_DATA_FORMAT_ASTC_3D_LDR = 0x00000031, 728 IMG_DATA_FORMAT_ASTC_3D_HDR = 0x00000032, 729 IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 0x00000033, 730 IMG_DATA_FORMAT_N_IN_16 = 0x00000034, 731 IMG_DATA_FORMAT_N_IN_16_16 = 0x00000035, 732 IMG_DATA_FORMAT_N_IN_16_16_16_16 = 0x00000036, 733 IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 0x00000037, 734 IMG_DATA_FORMAT_RESERVED_56 = 0x00000038, 735 IMG_DATA_FORMAT_4_4 = 0x00000039, 736 IMG_DATA_FORMAT_6_5_5 = 0x0000003a, 737 IMG_DATA_FORMAT_RESERVED_59 = 0x0000003b, 738 IMG_DATA_FORMAT_RESERVED_60 = 0x0000003c, 739 IMG_DATA_FORMAT_8_AS_32 = 0x0000003d, 740 IMG_DATA_FORMAT_8_AS_32_32 = 0x0000003e, 741 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f, 742 } IMG_DATA_FORMAT; 743 744 /* 745 * BUF_NUM_FORMAT enum 746 */ 747 748 typedef enum BUF_NUM_FORMAT { 749 BUF_NUM_FORMAT_UNORM = 0x00000000, 750 BUF_NUM_FORMAT_SNORM = 0x00000001, 751 BUF_NUM_FORMAT_USCALED = 0x00000002, 752 BUF_NUM_FORMAT_SSCALED = 0x00000003, 753 BUF_NUM_FORMAT_UINT = 0x00000004, 754 BUF_NUM_FORMAT_SINT = 0x00000005, 755 BUF_NUM_FORMAT_UNORM_UINT = 0x00000006, 756 BUF_NUM_FORMAT_FLOAT = 0x00000007, 757 } BUF_NUM_FORMAT; 758 759 /* 760 * IMG_NUM_FORMAT enum 761 */ 762 763 typedef enum IMG_NUM_FORMAT { 764 IMG_NUM_FORMAT_UNORM = 0x00000000, 765 IMG_NUM_FORMAT_SNORM = 0x00000001, 766 IMG_NUM_FORMAT_USCALED = 0x00000002, 767 IMG_NUM_FORMAT_SSCALED = 0x00000003, 768 IMG_NUM_FORMAT_UINT = 0x00000004, 769 IMG_NUM_FORMAT_SINT = 0x00000005, 770 IMG_NUM_FORMAT_UNORM_UINT = 0x00000006, 771 IMG_NUM_FORMAT_FLOAT = 0x00000007, 772 IMG_NUM_FORMAT_RESERVED_8 = 0x00000008, 773 IMG_NUM_FORMAT_SRGB = 0x00000009, 774 IMG_NUM_FORMAT_RESERVED_10 = 0x0000000a, 775 IMG_NUM_FORMAT_RESERVED_11 = 0x0000000b, 776 IMG_NUM_FORMAT_RESERVED_12 = 0x0000000c, 777 IMG_NUM_FORMAT_RESERVED_13 = 0x0000000d, 778 IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e, 779 IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f, 780 } IMG_NUM_FORMAT; 781 782 /* 783 * IMG_NUM_FORMAT_FMASK enum 784 */ 785 786 typedef enum IMG_NUM_FORMAT_FMASK { 787 IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000, 788 IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001, 789 IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002, 790 IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003, 791 IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004, 792 IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005, 793 IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006, 794 IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007, 795 IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008, 796 IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009, 797 IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a, 798 IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b, 799 IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c, 800 IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d, 801 IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e, 802 IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f, 803 } IMG_NUM_FORMAT_FMASK; 804 805 /* 806 * IMG_NUM_FORMAT_N_IN_16 enum 807 */ 808 809 typedef enum IMG_NUM_FORMAT_N_IN_16 { 810 IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000, 811 IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001, 812 IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002, 813 IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003, 814 IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004, 815 IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005, 816 IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006, 817 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007, 818 IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008, 819 IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009, 820 IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a, 821 IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b, 822 IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c, 823 IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d, 824 IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e, 825 IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f, 826 } IMG_NUM_FORMAT_N_IN_16; 827 828 /* 829 * IMG_NUM_FORMAT_ASTC_2D enum 830 */ 831 832 typedef enum IMG_NUM_FORMAT_ASTC_2D { 833 IMG_NUM_FORMAT_ASTC_2D_4x4 = 0x00000000, 834 IMG_NUM_FORMAT_ASTC_2D_5x4 = 0x00000001, 835 IMG_NUM_FORMAT_ASTC_2D_5x5 = 0x00000002, 836 IMG_NUM_FORMAT_ASTC_2D_6x5 = 0x00000003, 837 IMG_NUM_FORMAT_ASTC_2D_6x6 = 0x00000004, 838 IMG_NUM_FORMAT_ASTC_2D_8x5 = 0x00000005, 839 IMG_NUM_FORMAT_ASTC_2D_8x6 = 0x00000006, 840 IMG_NUM_FORMAT_ASTC_2D_8x8 = 0x00000007, 841 IMG_NUM_FORMAT_ASTC_2D_10x5 = 0x00000008, 842 IMG_NUM_FORMAT_ASTC_2D_10x6 = 0x00000009, 843 IMG_NUM_FORMAT_ASTC_2D_10x8 = 0x0000000a, 844 IMG_NUM_FORMAT_ASTC_2D_10x10 = 0x0000000b, 845 IMG_NUM_FORMAT_ASTC_2D_12x10 = 0x0000000c, 846 IMG_NUM_FORMAT_ASTC_2D_12x12 = 0x0000000d, 847 IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 0x0000000e, 848 IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 0x0000000f, 849 } IMG_NUM_FORMAT_ASTC_2D; 850 851 /* 852 * IMG_NUM_FORMAT_ASTC_3D enum 853 */ 854 855 typedef enum IMG_NUM_FORMAT_ASTC_3D { 856 IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0x00000000, 857 IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 0x00000001, 858 IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 0x00000002, 859 IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 0x00000003, 860 IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 0x00000004, 861 IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 0x00000005, 862 IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 0x00000006, 863 IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 0x00000007, 864 IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 0x00000008, 865 IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 0x00000009, 866 IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 0x0000000a, 867 IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 0x0000000b, 868 IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 0x0000000c, 869 IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 0x0000000d, 870 IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 0x0000000e, 871 IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 0x0000000f, 872 } IMG_NUM_FORMAT_ASTC_3D; 873 874 /* 875 * TileType enum 876 */ 877 878 typedef enum TileType { 879 ARRAY_COLOR_TILE = 0x00000000, 880 ARRAY_DEPTH_TILE = 0x00000001, 881 } TileType; 882 883 /* 884 * NonDispTilingOrder enum 885 */ 886 887 typedef enum NonDispTilingOrder { 888 ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000, 889 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001, 890 } NonDispTilingOrder; 891 892 /* 893 * MicroTileMode enum 894 */ 895 896 typedef enum MicroTileMode { 897 ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000, 898 ADDR_SURF_THIN_MICRO_TILING = 0x00000001, 899 ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002, 900 ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003, 901 ADDR_SURF_THICK_MICRO_TILING = 0x00000004, 902 } MicroTileMode; 903 904 /* 905 * TileSplit enum 906 */ 907 908 typedef enum TileSplit { 909 ADDR_SURF_TILE_SPLIT_64B = 0x00000000, 910 ADDR_SURF_TILE_SPLIT_128B = 0x00000001, 911 ADDR_SURF_TILE_SPLIT_256B = 0x00000002, 912 ADDR_SURF_TILE_SPLIT_512B = 0x00000003, 913 ADDR_SURF_TILE_SPLIT_1KB = 0x00000004, 914 ADDR_SURF_TILE_SPLIT_2KB = 0x00000005, 915 ADDR_SURF_TILE_SPLIT_4KB = 0x00000006, 916 } TileSplit; 917 918 /* 919 * SampleSplit enum 920 */ 921 922 typedef enum SampleSplit { 923 ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000, 924 ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001, 925 ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002, 926 ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003, 927 } SampleSplit; 928 929 /* 930 * PipeConfig enum 931 */ 932 933 typedef enum PipeConfig { 934 ADDR_SURF_P2 = 0x00000000, 935 ADDR_SURF_P2_RESERVED0 = 0x00000001, 936 ADDR_SURF_P2_RESERVED1 = 0x00000002, 937 ADDR_SURF_P2_RESERVED2 = 0x00000003, 938 ADDR_SURF_P4_8x16 = 0x00000004, 939 ADDR_SURF_P4_16x16 = 0x00000005, 940 ADDR_SURF_P4_16x32 = 0x00000006, 941 ADDR_SURF_P4_32x32 = 0x00000007, 942 ADDR_SURF_P8_16x16_8x16 = 0x00000008, 943 ADDR_SURF_P8_16x32_8x16 = 0x00000009, 944 ADDR_SURF_P8_32x32_8x16 = 0x0000000a, 945 ADDR_SURF_P8_16x32_16x16 = 0x0000000b, 946 ADDR_SURF_P8_32x32_16x16 = 0x0000000c, 947 ADDR_SURF_P8_32x32_16x32 = 0x0000000d, 948 ADDR_SURF_P8_32x64_32x32 = 0x0000000e, 949 ADDR_SURF_P8_RESERVED0 = 0x0000000f, 950 ADDR_SURF_P16_32x32_8x16 = 0x00000010, 951 ADDR_SURF_P16_32x32_16x16 = 0x00000011, 952 } PipeConfig; 953 954 /* 955 * SeEnable enum 956 */ 957 958 typedef enum SeEnable { 959 ADDR_CONFIG_DISABLE_SE = 0x00000000, 960 ADDR_CONFIG_ENABLE_SE = 0x00000001, 961 } SeEnable; 962 963 /* 964 * NumBanks enum 965 */ 966 967 typedef enum NumBanks { 968 ADDR_SURF_2_BANK = 0x00000000, 969 ADDR_SURF_4_BANK = 0x00000001, 970 ADDR_SURF_8_BANK = 0x00000002, 971 ADDR_SURF_16_BANK = 0x00000003, 972 } NumBanks; 973 974 /* 975 * BankWidth enum 976 */ 977 978 typedef enum BankWidth { 979 ADDR_SURF_BANK_WIDTH_1 = 0x00000000, 980 ADDR_SURF_BANK_WIDTH_2 = 0x00000001, 981 ADDR_SURF_BANK_WIDTH_4 = 0x00000002, 982 ADDR_SURF_BANK_WIDTH_8 = 0x00000003, 983 } BankWidth; 984 985 /* 986 * BankHeight enum 987 */ 988 989 typedef enum BankHeight { 990 ADDR_SURF_BANK_HEIGHT_1 = 0x00000000, 991 ADDR_SURF_BANK_HEIGHT_2 = 0x00000001, 992 ADDR_SURF_BANK_HEIGHT_4 = 0x00000002, 993 ADDR_SURF_BANK_HEIGHT_8 = 0x00000003, 994 } BankHeight; 995 996 /* 997 * BankWidthHeight enum 998 */ 999 1000 typedef enum BankWidthHeight { 1001 ADDR_SURF_BANK_WH_1 = 0x00000000, 1002 ADDR_SURF_BANK_WH_2 = 0x00000001, 1003 ADDR_SURF_BANK_WH_4 = 0x00000002, 1004 ADDR_SURF_BANK_WH_8 = 0x00000003, 1005 } BankWidthHeight; 1006 1007 /* 1008 * MacroTileAspect enum 1009 */ 1010 1011 typedef enum MacroTileAspect { 1012 ADDR_SURF_MACRO_ASPECT_1 = 0x00000000, 1013 ADDR_SURF_MACRO_ASPECT_2 = 0x00000001, 1014 ADDR_SURF_MACRO_ASPECT_4 = 0x00000002, 1015 ADDR_SURF_MACRO_ASPECT_8 = 0x00000003, 1016 } MacroTileAspect; 1017 1018 /* 1019 * GATCL1RequestType enum 1020 */ 1021 1022 typedef enum GATCL1RequestType { 1023 GATCL1_TYPE_NORMAL = 0x00000000, 1024 GATCL1_TYPE_SHOOTDOWN = 0x00000001, 1025 GATCL1_TYPE_BYPASS = 0x00000002, 1026 } GATCL1RequestType; 1027 1028 /* 1029 * UTCL1RequestType enum 1030 */ 1031 1032 typedef enum UTCL1RequestType { 1033 UTCL1_TYPE_NORMAL = 0x00000000, 1034 UTCL1_TYPE_SHOOTDOWN = 0x00000001, 1035 UTCL1_TYPE_BYPASS = 0x00000002, 1036 } UTCL1RequestType; 1037 1038 /* 1039 * UTCL1FaultType enum 1040 */ 1041 1042 typedef enum UTCL1FaultType { 1043 UTCL1_XNACK_SUCCESS = 0x00000000, 1044 UTCL1_XNACK_RETRY = 0x00000001, 1045 UTCL1_XNACK_PRT = 0x00000002, 1046 UTCL1_XNACK_NO_RETRY = 0x00000003, 1047 } UTCL1FaultType; 1048 1049 /* 1050 * TCC_CACHE_POLICIES enum 1051 */ 1052 1053 typedef enum TCC_CACHE_POLICIES { 1054 TCC_CACHE_POLICY_LRU = 0x00000000, 1055 TCC_CACHE_POLICY_STREAM = 0x00000001, 1056 } TCC_CACHE_POLICIES; 1057 1058 /* 1059 * MTYPE enum 1060 */ 1061 1062 typedef enum MTYPE { 1063 MTYPE_NC = 0x00000000, 1064 MTYPE_WC = 0x00000001, 1065 MTYPE_CC = 0x00000002, 1066 MTYPE_UC = 0x00000003, 1067 } MTYPE; 1068 1069 /* 1070 * RMI_CID enum 1071 */ 1072 1073 typedef enum RMI_CID { 1074 RMI_CID_CC = 0x00000000, 1075 RMI_CID_FC = 0x00000001, 1076 RMI_CID_CM = 0x00000002, 1077 RMI_CID_DC = 0x00000003, 1078 RMI_CID_Z = 0x00000004, 1079 RMI_CID_S = 0x00000005, 1080 RMI_CID_TILE = 0x00000006, 1081 RMI_CID_ZPCPSD = 0x00000007, 1082 } RMI_CID; 1083 1084 /* 1085 * PERFMON_COUNTER_MODE enum 1086 */ 1087 1088 typedef enum PERFMON_COUNTER_MODE { 1089 PERFMON_COUNTER_MODE_ACCUM = 0x00000000, 1090 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001, 1091 PERFMON_COUNTER_MODE_MAX = 0x00000002, 1092 PERFMON_COUNTER_MODE_DIRTY = 0x00000003, 1093 PERFMON_COUNTER_MODE_SAMPLE = 0x00000004, 1094 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005, 1095 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006, 1096 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007, 1097 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008, 1098 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009, 1099 PERFMON_COUNTER_MODE_RESERVED = 0x0000000f, 1100 } PERFMON_COUNTER_MODE; 1101 1102 /* 1103 * PERFMON_SPM_MODE enum 1104 */ 1105 1106 typedef enum PERFMON_SPM_MODE { 1107 PERFMON_SPM_MODE_OFF = 0x00000000, 1108 PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001, 1109 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002, 1110 PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003, 1111 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004, 1112 PERFMON_SPM_MODE_RESERVED_5 = 0x00000005, 1113 PERFMON_SPM_MODE_RESERVED_6 = 0x00000006, 1114 PERFMON_SPM_MODE_RESERVED_7 = 0x00000007, 1115 PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008, 1116 PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009, 1117 PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a, 1118 } PERFMON_SPM_MODE; 1119 1120 /* 1121 * SurfaceTiling enum 1122 */ 1123 1124 typedef enum SurfaceTiling { 1125 ARRAY_LINEAR = 0x00000000, 1126 ARRAY_TILED = 0x00000001, 1127 } SurfaceTiling; 1128 1129 /* 1130 * SurfaceArray enum 1131 */ 1132 1133 typedef enum SurfaceArray { 1134 ARRAY_1D = 0x00000000, 1135 ARRAY_2D = 0x00000001, 1136 ARRAY_3D = 0x00000002, 1137 ARRAY_3D_SLICE = 0x00000003, 1138 } SurfaceArray; 1139 1140 /* 1141 * ColorArray enum 1142 */ 1143 1144 typedef enum ColorArray { 1145 ARRAY_2D_ALT_COLOR = 0x00000000, 1146 ARRAY_2D_COLOR = 0x00000001, 1147 ARRAY_3D_SLICE_COLOR = 0x00000003, 1148 } ColorArray; 1149 1150 /* 1151 * DepthArray enum 1152 */ 1153 1154 typedef enum DepthArray { 1155 ARRAY_2D_ALT_DEPTH = 0x00000000, 1156 ARRAY_2D_DEPTH = 0x00000001, 1157 } DepthArray; 1158 1159 /* 1160 * ENUM_NUM_SIMD_PER_CU enum 1161 */ 1162 1163 typedef enum ENUM_NUM_SIMD_PER_CU { 1164 NUM_SIMD_PER_CU = 0x00000004, 1165 } ENUM_NUM_SIMD_PER_CU; 1166 1167 /* 1168 * DSM_ENABLE_ERROR_INJECT enum 1169 */ 1170 1171 typedef enum DSM_ENABLE_ERROR_INJECT { 1172 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000, 1173 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001, 1174 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002, 1175 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003, 1176 } DSM_ENABLE_ERROR_INJECT; 1177 1178 /* 1179 * DSM_SELECT_INJECT_DELAY enum 1180 */ 1181 1182 typedef enum DSM_SELECT_INJECT_DELAY { 1183 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000, 1184 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001, 1185 } DSM_SELECT_INJECT_DELAY; 1186 1187 /* 1188 * DSM_DATA_SEL enum 1189 */ 1190 1191 typedef enum DSM_DATA_SEL { 1192 DSM_DATA_SEL_DISABLE = 0x00000000, 1193 DSM_DATA_SEL_0 = 0x00000001, 1194 DSM_DATA_SEL_1 = 0x00000002, 1195 DSM_DATA_SEL_BOTH = 0x00000003, 1196 } DSM_DATA_SEL; 1197 1198 /* 1199 * DSM_SINGLE_WRITE enum 1200 */ 1201 1202 typedef enum DSM_SINGLE_WRITE { 1203 DSM_SINGLE_WRITE_DIS = 0x00000000, 1204 DSM_SINGLE_WRITE_EN = 0x00000001, 1205 } DSM_SINGLE_WRITE; 1206 1207 /* 1208 * SWIZZLE_TYPE_ENUM enum 1209 */ 1210 1211 typedef enum SWIZZLE_TYPE_ENUM { 1212 SW_Z = 0x00000000, 1213 SW_S = 0x00000001, 1214 SW_D = 0x00000002, 1215 SW_R = 0x00000003, 1216 SW_L = 0x00000004, 1217 } SWIZZLE_TYPE_ENUM; 1218 1219 /* 1220 * TC_MICRO_TILE_MODE enum 1221 */ 1222 1223 typedef enum TC_MICRO_TILE_MODE { 1224 MICRO_TILE_MODE_LINEAR = 0x00000000, 1225 MICRO_TILE_MODE_ROTATED = 0x00000001, 1226 MICRO_TILE_MODE_STD_2D = 0x00000002, 1227 MICRO_TILE_MODE_STD_3D = 0x00000003, 1228 MICRO_TILE_MODE_DISPLAY_2D = 0x00000004, 1229 MICRO_TILE_MODE_DISPLAY_3D = 0x00000005, 1230 MICRO_TILE_MODE_Z_2D = 0x00000006, 1231 MICRO_TILE_MODE_Z_3D = 0x00000007, 1232 } TC_MICRO_TILE_MODE; 1233 1234 /* 1235 * SWIZZLE_MODE_ENUM enum 1236 */ 1237 1238 typedef enum SWIZZLE_MODE_ENUM { 1239 SW_LINEAR = 0x00000000, 1240 SW_256B_S = 0x00000001, 1241 SW_256B_D = 0x00000002, 1242 SW_256B_R = 0x00000003, 1243 SW_4KB_Z = 0x00000004, 1244 SW_4KB_S = 0x00000005, 1245 SW_4KB_D = 0x00000006, 1246 SW_4KB_R = 0x00000007, 1247 SW_64KB_Z = 0x00000008, 1248 SW_64KB_S = 0x00000009, 1249 SW_64KB_D = 0x0000000a, 1250 SW_64KB_R = 0x0000000b, 1251 SW_VAR_Z = 0x0000000c, 1252 SW_VAR_S = 0x0000000d, 1253 SW_VAR_D = 0x0000000e, 1254 SW_VAR_R = 0x0000000f, 1255 SW_RESERVED_16 = 0x00000010, 1256 SW_RESERVED_17 = 0x00000011, 1257 SW_RESERVED_18 = 0x00000012, 1258 SW_RESERVED_19 = 0x00000013, 1259 SW_4KB_Z_X = 0x00000014, 1260 SW_4KB_S_X = 0x00000015, 1261 SW_4KB_D_X = 0x00000016, 1262 SW_4KB_R_X = 0x00000017, 1263 SW_64KB_Z_X = 0x00000018, 1264 SW_64KB_S_X = 0x00000019, 1265 SW_64KB_D_X = 0x0000001a, 1266 SW_64KB_R_X = 0x0000001b, 1267 SW_VAR_Z_X = 0x0000001c, 1268 SW_VAR_S_X = 0x0000001d, 1269 SW_VAR_D_X = 0x0000001e, 1270 SW_VAR_R_X = 0x0000001f, 1271 } SWIZZLE_MODE_ENUM; 1272 1273 /******************************************************* 1274 * IH Enums 1275 *******************************************************/ 1276 1277 /* 1278 * IH_PERF_SEL enum 1279 */ 1280 1281 typedef enum IH_PERF_SEL { 1282 IH_PERF_SEL_CYCLE = 0x00000000, 1283 IH_PERF_SEL_IDLE = 0x00000001, 1284 IH_PERF_SEL_INPUT_IDLE = 0x00000002, 1285 IH_PERF_SEL_BUFFER_IDLE = 0x00000003, 1286 IH_PERF_SEL_RB0_FULL = 0x00000004, 1287 IH_PERF_SEL_RB0_OVERFLOW = 0x00000005, 1288 IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006, 1289 IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007, 1290 IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008, 1291 IH_PERF_SEL_MC_WR_IDLE = 0x00000009, 1292 IH_PERF_SEL_MC_WR_COUNT = 0x0000000a, 1293 IH_PERF_SEL_MC_WR_STALL = 0x0000000b, 1294 IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c, 1295 IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d, 1296 IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e, 1297 IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f, 1298 IH_PERF_SEL_RB1_FULL = 0x00000010, 1299 IH_PERF_SEL_RB1_OVERFLOW = 0x00000011, 1300 Reserved18 = 0x00000012, 1301 IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013, 1302 IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014, 1303 IH_PERF_SEL_RB2_FULL = 0x00000015, 1304 IH_PERF_SEL_RB2_OVERFLOW = 0x00000016, 1305 Reserved23 = 0x00000017, 1306 IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018, 1307 IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019, 1308 Reserved26 = 0x0000001a, 1309 Reserved27 = 0x0000001b, 1310 Reserved28 = 0x0000001c, 1311 Reserved29 = 0x0000001d, 1312 IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001e, 1313 IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001f, 1314 IH_PERF_SEL_RB0_FULL_VF2 = 0x00000020, 1315 IH_PERF_SEL_RB0_FULL_VF3 = 0x00000021, 1316 IH_PERF_SEL_RB0_FULL_VF4 = 0x00000022, 1317 IH_PERF_SEL_RB0_FULL_VF5 = 0x00000023, 1318 IH_PERF_SEL_RB0_FULL_VF6 = 0x00000024, 1319 IH_PERF_SEL_RB0_FULL_VF7 = 0x00000025, 1320 IH_PERF_SEL_RB0_FULL_VF8 = 0x00000026, 1321 IH_PERF_SEL_RB0_FULL_VF9 = 0x00000027, 1322 IH_PERF_SEL_RB0_FULL_VF10 = 0x00000028, 1323 IH_PERF_SEL_RB0_FULL_VF11 = 0x00000029, 1324 IH_PERF_SEL_RB0_FULL_VF12 = 0x0000002a, 1325 IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002b, 1326 IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002c, 1327 IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002d, 1328 IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000002e, 1329 IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000002f, 1330 IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x00000030, 1331 IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x00000031, 1332 IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000032, 1333 IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000033, 1334 IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000034, 1335 IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000035, 1336 IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000036, 1337 IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000037, 1338 IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000038, 1339 IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000039, 1340 IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x0000003a, 1341 IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x0000003b, 1342 IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000003c, 1343 IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000003d, 1344 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000003e, 1345 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000003f, 1346 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x00000040, 1347 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x00000041, 1348 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x00000042, 1349 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000043, 1350 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000044, 1351 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000045, 1352 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000046, 1353 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000047, 1354 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000048, 1355 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000049, 1356 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x0000004a, 1357 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x0000004b, 1358 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x0000004c, 1359 IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000004d, 1360 IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000004e, 1361 IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000004f, 1362 IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x00000050, 1363 IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x00000051, 1364 IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x00000052, 1365 IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x00000053, 1366 IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000054, 1367 IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000055, 1368 IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000056, 1369 IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000057, 1370 IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000058, 1371 IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000059, 1372 IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x0000005a, 1373 IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x0000005b, 1374 IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x0000005c, 1375 IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x0000005d, 1376 IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x0000005e, 1377 IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000005f, 1378 IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x00000060, 1379 IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x00000061, 1380 IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x00000062, 1381 IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x00000063, 1382 IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x00000064, 1383 IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x00000065, 1384 IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x00000066, 1385 IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x00000067, 1386 IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x00000068, 1387 IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x00000069, 1388 IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x0000006a, 1389 IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x0000006b, 1390 IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x0000006c, 1391 IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x0000006d, 1392 IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x0000006e, 1393 IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x0000006f, 1394 IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x00000070, 1395 IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x00000071, 1396 IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x00000072, 1397 IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x00000073, 1398 IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x00000074, 1399 IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x00000075, 1400 IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x00000076, 1401 IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x00000077, 1402 IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x00000078, 1403 IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x00000079, 1404 IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x0000007a, 1405 IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x0000007b, 1406 IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x0000007c, 1407 IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x0000007d, 1408 IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x0000007e, 1409 IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x0000007f, 1410 IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x00000080, 1411 IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x00000081, 1412 IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x00000082, 1413 IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x00000083, 1414 IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x00000084, 1415 IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x00000085, 1416 IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x00000086, 1417 IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x00000087, 1418 IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x00000088, 1419 IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x00000089, 1420 IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x0000008a, 1421 IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x0000008b, 1422 IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x0000008c, 1423 IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x0000008d, 1424 Reserved142 = 0x0000008e, 1425 Reserved143 = 0x0000008f, 1426 Reserved144 = 0x00000090, 1427 Reserved145 = 0x00000091, 1428 Reserved146 = 0x00000092, 1429 Reserved147 = 0x00000093, 1430 Reserved148 = 0x00000094, 1431 Reserved149 = 0x00000095, 1432 IH_PERF_SEL_CLIENT0_INT = 0x00000096, 1433 IH_PERF_SEL_CLIENT1_INT = 0x00000097, 1434 IH_PERF_SEL_CLIENT2_INT = 0x00000098, 1435 IH_PERF_SEL_CLIENT3_INT = 0x00000099, 1436 IH_PERF_SEL_CLIENT4_INT = 0x0000009a, 1437 IH_PERF_SEL_CLIENT5_INT = 0x0000009b, 1438 IH_PERF_SEL_CLIENT6_INT = 0x0000009c, 1439 IH_PERF_SEL_CLIENT7_INT = 0x0000009d, 1440 IH_PERF_SEL_CLIENT8_INT = 0x0000009e, 1441 IH_PERF_SEL_CLIENT9_INT = 0x0000009f, 1442 IH_PERF_SEL_CLIENT10_INT = 0x000000a0, 1443 IH_PERF_SEL_CLIENT11_INT = 0x000000a1, 1444 IH_PERF_SEL_CLIENT12_INT = 0x000000a2, 1445 IH_PERF_SEL_CLIENT13_INT = 0x000000a3, 1446 IH_PERF_SEL_CLIENT14_INT = 0x000000a4, 1447 IH_PERF_SEL_CLIENT15_INT = 0x000000a5, 1448 IH_PERF_SEL_CLIENT16_INT = 0x000000a6, 1449 IH_PERF_SEL_CLIENT17_INT = 0x000000a7, 1450 IH_PERF_SEL_CLIENT18_INT = 0x000000a8, 1451 IH_PERF_SEL_CLIENT19_INT = 0x000000a9, 1452 IH_PERF_SEL_CLIENT20_INT = 0x000000aa, 1453 IH_PERF_SEL_CLIENT21_INT = 0x000000ab, 1454 IH_PERF_SEL_CLIENT22_INT = 0x000000ac, 1455 IH_PERF_SEL_CLIENT23_INT = 0x000000ad, 1456 IH_PERF_SEL_CLIENT24_INT = 0x000000ae, 1457 IH_PERF_SEL_CLIENT25_INT = 0x000000af, 1458 IH_PERF_SEL_CLIENT26_INT = 0x000000b0, 1459 IH_PERF_SEL_CLIENT27_INT = 0x000000b1, 1460 IH_PERF_SEL_CLIENT28_INT = 0x000000b2, 1461 IH_PERF_SEL_CLIENT29_INT = 0x000000b3, 1462 IH_PERF_SEL_CLIENT30_INT = 0x000000b4, 1463 IH_PERF_SEL_CLIENT31_INT = 0x000000b5, 1464 Reserved182 = 0x000000b6, 1465 Reserved183 = 0x000000b7, 1466 Reserved184 = 0x000000b8, 1467 Reserved185 = 0x000000b9, 1468 Reserved186 = 0x000000ba, 1469 Reserved187 = 0x000000bb, 1470 Reserved188 = 0x000000bc, 1471 Reserved189 = 0x000000bd, 1472 Reserved190 = 0x000000be, 1473 Reserved191 = 0x000000bf, 1474 Reserved192 = 0x000000c0, 1475 Reserved193 = 0x000000c1, 1476 Reserved194 = 0x000000c2, 1477 Reserved195 = 0x000000c3, 1478 Reserved196 = 0x000000c4, 1479 Reserved197 = 0x000000c5, 1480 Reserved198 = 0x000000c6, 1481 Reserved199 = 0x000000c7, 1482 Reserved200 = 0x000000c8, 1483 Reserved201 = 0x000000c9, 1484 Reserved202 = 0x000000ca, 1485 Reserved203 = 0x000000cb, 1486 Reserved204 = 0x000000cc, 1487 Reserved205 = 0x000000cd, 1488 Reserved206 = 0x000000ce, 1489 Reserved207 = 0x000000cf, 1490 Reserved208 = 0x000000d0, 1491 Reserved209 = 0x000000d1, 1492 Reserved210 = 0x000000d2, 1493 Reserved211 = 0x000000d3, 1494 Reserved212 = 0x000000d4, 1495 Reserved213 = 0x000000d5, 1496 Reserved214 = 0x000000d6, 1497 Reserved215 = 0x000000d7, 1498 Reserved216 = 0x000000d8, 1499 Reserved217 = 0x000000d9, 1500 Reserved218 = 0x000000da, 1501 Reserved219 = 0x000000db, 1502 IH_PERF_SEL_RB1_FULL_VF0 = 0x000000dc, 1503 IH_PERF_SEL_RB1_FULL_VF1 = 0x000000dd, 1504 IH_PERF_SEL_RB1_FULL_VF2 = 0x000000de, 1505 IH_PERF_SEL_RB1_FULL_VF3 = 0x000000df, 1506 IH_PERF_SEL_RB1_FULL_VF4 = 0x000000e0, 1507 IH_PERF_SEL_RB1_FULL_VF5 = 0x000000e1, 1508 IH_PERF_SEL_RB1_FULL_VF6 = 0x000000e2, 1509 IH_PERF_SEL_RB1_FULL_VF7 = 0x000000e3, 1510 IH_PERF_SEL_RB1_FULL_VF8 = 0x000000e4, 1511 IH_PERF_SEL_RB1_FULL_VF9 = 0x000000e5, 1512 IH_PERF_SEL_RB1_FULL_VF10 = 0x000000e6, 1513 IH_PERF_SEL_RB1_FULL_VF11 = 0x000000e7, 1514 IH_PERF_SEL_RB1_FULL_VF12 = 0x000000e8, 1515 IH_PERF_SEL_RB1_FULL_VF13 = 0x000000e9, 1516 IH_PERF_SEL_RB1_FULL_VF14 = 0x000000ea, 1517 IH_PERF_SEL_RB1_FULL_VF15 = 0x000000eb, 1518 IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x000000ec, 1519 IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x000000ed, 1520 IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x000000ee, 1521 IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x000000ef, 1522 IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x000000f0, 1523 IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x000000f1, 1524 IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x000000f2, 1525 IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x000000f3, 1526 IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x000000f4, 1527 IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x000000f5, 1528 IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x000000f6, 1529 IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x000000f7, 1530 IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x000000f8, 1531 IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x000000f9, 1532 IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x000000fa, 1533 IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x000000fb, 1534 Reserved252 = 0x000000fc, 1535 Reserved253 = 0x000000fd, 1536 Reserved254 = 0x000000fe, 1537 Reserved255 = 0x000000ff, 1538 Reserved256 = 0x00000100, 1539 Reserved257 = 0x00000101, 1540 Reserved258 = 0x00000102, 1541 Reserved259 = 0x00000103, 1542 Reserved260 = 0x00000104, 1543 Reserved261 = 0x00000105, 1544 Reserved262 = 0x00000106, 1545 Reserved263 = 0x00000107, 1546 Reserved264 = 0x00000108, 1547 Reserved265 = 0x00000109, 1548 Reserved266 = 0x0000010a, 1549 Reserved267 = 0x0000010b, 1550 IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x0000010c, 1551 IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x0000010d, 1552 IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x0000010e, 1553 IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x0000010f, 1554 IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x00000110, 1555 IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x00000111, 1556 IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x00000112, 1557 IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x00000113, 1558 IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x00000114, 1559 IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x00000115, 1560 IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x00000116, 1561 IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x00000117, 1562 IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x00000118, 1563 IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x00000119, 1564 IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x0000011a, 1565 IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x0000011b, 1566 IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x0000011c, 1567 IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x0000011d, 1568 IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x0000011e, 1569 IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x0000011f, 1570 IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x00000120, 1571 IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x00000121, 1572 IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x00000122, 1573 IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x00000123, 1574 IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x00000124, 1575 IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x00000125, 1576 IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x00000126, 1577 IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x00000127, 1578 IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x00000128, 1579 IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x00000129, 1580 IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x0000012a, 1581 IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x0000012b, 1582 Reserved300 = 0x0000012c, 1583 Reserved301 = 0x0000012d, 1584 Reserved302 = 0x0000012e, 1585 Reserved303 = 0x0000012f, 1586 Reserved304 = 0x00000130, 1587 Reserved305 = 0x00000131, 1588 Reserved306 = 0x00000132, 1589 Reserved307 = 0x00000133, 1590 Reserved308 = 0x00000134, 1591 Reserved309 = 0x00000135, 1592 Reserved310 = 0x00000136, 1593 Reserved311 = 0x00000137, 1594 Reserved312 = 0x00000138, 1595 Reserved313 = 0x00000139, 1596 Reserved314 = 0x0000013a, 1597 Reserved315 = 0x0000013b, 1598 Reserved316 = 0x0000013c, 1599 Reserved317 = 0x0000013d, 1600 Reserved318 = 0x0000013e, 1601 Reserved319 = 0x0000013f, 1602 Reserved320 = 0x00000140, 1603 Reserved321 = 0x00000141, 1604 Reserved322 = 0x00000142, 1605 Reserved323 = 0x00000143, 1606 Reserved324 = 0x00000144, 1607 Reserved325 = 0x00000145, 1608 Reserved326 = 0x00000146, 1609 Reserved327 = 0x00000147, 1610 Reserved328 = 0x00000148, 1611 Reserved329 = 0x00000149, 1612 Reserved330 = 0x0000014a, 1613 Reserved331 = 0x0000014b, 1614 IH_PERF_SEL_RB2_FULL_VF0 = 0x0000014c, 1615 IH_PERF_SEL_RB2_FULL_VF1 = 0x0000014d, 1616 IH_PERF_SEL_RB2_FULL_VF2 = 0x0000014e, 1617 IH_PERF_SEL_RB2_FULL_VF3 = 0x0000014f, 1618 IH_PERF_SEL_RB2_FULL_VF4 = 0x00000150, 1619 IH_PERF_SEL_RB2_FULL_VF5 = 0x00000151, 1620 IH_PERF_SEL_RB2_FULL_VF6 = 0x00000152, 1621 IH_PERF_SEL_RB2_FULL_VF7 = 0x00000153, 1622 IH_PERF_SEL_RB2_FULL_VF8 = 0x00000154, 1623 IH_PERF_SEL_RB2_FULL_VF9 = 0x00000155, 1624 IH_PERF_SEL_RB2_FULL_VF10 = 0x00000156, 1625 IH_PERF_SEL_RB2_FULL_VF11 = 0x00000157, 1626 IH_PERF_SEL_RB2_FULL_VF12 = 0x00000158, 1627 IH_PERF_SEL_RB2_FULL_VF13 = 0x00000159, 1628 IH_PERF_SEL_RB2_FULL_VF14 = 0x0000015a, 1629 IH_PERF_SEL_RB2_FULL_VF15 = 0x0000015b, 1630 IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x0000015c, 1631 IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x0000015d, 1632 IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x0000015e, 1633 IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x0000015f, 1634 IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x00000160, 1635 IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x00000161, 1636 IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x00000162, 1637 IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x00000163, 1638 IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x00000164, 1639 IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x00000165, 1640 IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x00000166, 1641 IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x00000167, 1642 IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x00000168, 1643 IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x00000169, 1644 IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x0000016a, 1645 IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x0000016b, 1646 Reserved364 = 0x0000016c, 1647 Reserved365 = 0x0000016d, 1648 Reserved366 = 0x0000016e, 1649 Reserved367 = 0x0000016f, 1650 Reserved368 = 0x00000170, 1651 Reserved369 = 0x00000171, 1652 Reserved370 = 0x00000172, 1653 Reserved371 = 0x00000173, 1654 Reserved372 = 0x00000174, 1655 Reserved373 = 0x00000175, 1656 Reserved374 = 0x00000176, 1657 Reserved375 = 0x00000177, 1658 Reserved376 = 0x00000178, 1659 Reserved377 = 0x00000179, 1660 Reserved378 = 0x0000017a, 1661 Reserved379 = 0x0000017b, 1662 IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x0000017c, 1663 IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x0000017d, 1664 IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x0000017e, 1665 IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x0000017f, 1666 IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x00000180, 1667 IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x00000181, 1668 IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x00000182, 1669 IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x00000183, 1670 IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x00000184, 1671 IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x00000185, 1672 IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x00000186, 1673 IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x00000187, 1674 IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x00000188, 1675 IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x00000189, 1676 IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x0000018a, 1677 IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x0000018b, 1678 IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x0000018c, 1679 IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x0000018d, 1680 IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x0000018e, 1681 IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x0000018f, 1682 IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x00000190, 1683 IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x00000191, 1684 IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x00000192, 1685 IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x00000193, 1686 IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x00000194, 1687 IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x00000195, 1688 IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x00000196, 1689 IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x00000197, 1690 IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x00000198, 1691 IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x00000199, 1692 IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x0000019a, 1693 IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x0000019b, 1694 Reserved412 = 0x0000019c, 1695 Reserved413 = 0x0000019d, 1696 Reserved414 = 0x0000019e, 1697 Reserved415 = 0x0000019f, 1698 Reserved416 = 0x000001a0, 1699 Reserved417 = 0x000001a1, 1700 Reserved418 = 0x000001a2, 1701 Reserved419 = 0x000001a3, 1702 Reserved420 = 0x000001a4, 1703 Reserved421 = 0x000001a5, 1704 Reserved422 = 0x000001a6, 1705 Reserved423 = 0x000001a7, 1706 Reserved424 = 0x000001a8, 1707 Reserved425 = 0x000001a9, 1708 Reserved426 = 0x000001aa, 1709 Reserved427 = 0x000001ab, 1710 Reserved428 = 0x000001ac, 1711 Reserved429 = 0x000001ad, 1712 Reserved430 = 0x000001ae, 1713 Reserved431 = 0x000001af, 1714 Reserved432 = 0x000001b0, 1715 Reserved433 = 0x000001b1, 1716 Reserved434 = 0x000001b2, 1717 Reserved435 = 0x000001b3, 1718 Reserved436 = 0x000001b4, 1719 Reserved437 = 0x000001b5, 1720 Reserved438 = 0x000001b6, 1721 Reserved439 = 0x000001b7, 1722 Reserved440 = 0x000001b8, 1723 Reserved441 = 0x000001b9, 1724 Reserved442 = 0x000001ba, 1725 Reserved443 = 0x000001bb, 1726 Reserved444 = 0x000001bc, 1727 Reserved445 = 0x000001bd, 1728 Reserved446 = 0x000001be, 1729 Reserved447 = 0x000001bf, 1730 Reserved448 = 0x000001c0, 1731 Reserved449 = 0x000001c1, 1732 Reserved450 = 0x000001c2, 1733 Reserved451 = 0x000001c3, 1734 Reserved452 = 0x000001c4, 1735 Reserved453 = 0x000001c5, 1736 Reserved454 = 0x000001c6, 1737 Reserved455 = 0x000001c7, 1738 Reserved456 = 0x000001c8, 1739 Reserved457 = 0x000001c9, 1740 Reserved458 = 0x000001ca, 1741 Reserved459 = 0x000001cb, 1742 Reserved460 = 0x000001cc, 1743 Reserved461 = 0x000001cd, 1744 Reserved462 = 0x000001ce, 1745 Reserved463 = 0x000001cf, 1746 Reserved464 = 0x000001d0, 1747 Reserved465 = 0x000001d1, 1748 Reserved466 = 0x000001d2, 1749 Reserved467 = 0x000001d3, 1750 Reserved468 = 0x000001d4, 1751 Reserved469 = 0x000001d5, 1752 Reserved470 = 0x000001d6, 1753 Reserved471 = 0x000001d7, 1754 Reserved472 = 0x000001d8, 1755 Reserved473 = 0x000001d9, 1756 Reserved474 = 0x000001da, 1757 Reserved475 = 0x000001db, 1758 Reserved476 = 0x000001dc, 1759 Reserved477 = 0x000001dd, 1760 Reserved478 = 0x000001de, 1761 Reserved479 = 0x000001df, 1762 Reserved480 = 0x000001e0, 1763 Reserved481 = 0x000001e1, 1764 Reserved482 = 0x000001e2, 1765 Reserved483 = 0x000001e3, 1766 Reserved484 = 0x000001e4, 1767 Reserved485 = 0x000001e5, 1768 Reserved486 = 0x000001e6, 1769 Reserved487 = 0x000001e7, 1770 Reserved488 = 0x000001e8, 1771 Reserved489 = 0x000001e9, 1772 Reserved490 = 0x000001ea, 1773 Reserved491 = 0x000001eb, 1774 Reserved492 = 0x000001ec, 1775 Reserved493 = 0x000001ed, 1776 Reserved494 = 0x000001ee, 1777 Reserved495 = 0x000001ef, 1778 Reserved496 = 0x000001f0, 1779 Reserved497 = 0x000001f1, 1780 Reserved498 = 0x000001f2, 1781 Reserved499 = 0x000001f3, 1782 Reserved500 = 0x000001f4, 1783 Reserved501 = 0x000001f5, 1784 Reserved502 = 0x000001f6, 1785 Reserved503 = 0x000001f7, 1786 Reserved504 = 0x000001f8, 1787 Reserved505 = 0x000001f9, 1788 Reserved506 = 0x000001fa, 1789 Reserved507 = 0x000001fb, 1790 Reserved508 = 0x000001fc, 1791 Reserved509 = 0x000001fd, 1792 Reserved510 = 0x000001fe, 1793 Reserved511 = 0x000001ff, 1794 } IH_PERF_SEL; 1795 1796 /******************************************************* 1797 * SEM Enums 1798 *******************************************************/ 1799 1800 /* 1801 * SEM_PERF_SEL enum 1802 */ 1803 1804 typedef enum SEM_PERF_SEL { 1805 SEM_PERF_SEL_CYCLE = 0x00000000, 1806 SEM_PERF_SEL_IDLE = 0x00000001, 1807 SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002, 1808 SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003, 1809 SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004, 1810 SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005, 1811 SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006, 1812 SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007, 1813 SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008, 1814 SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009, 1815 SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a, 1816 SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b, 1817 SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c, 1818 SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d, 1819 SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e, 1820 SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f, 1821 SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010, 1822 SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011, 1823 SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012, 1824 SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013, 1825 SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014, 1826 SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015, 1827 SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016, 1828 SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017, 1829 SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018, 1830 SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019, 1831 SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a, 1832 SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b, 1833 SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c, 1834 SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d, 1835 SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e, 1836 SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f, 1837 SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020, 1838 SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021, 1839 SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022, 1840 SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023, 1841 SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024, 1842 SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025, 1843 SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026, 1844 SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027, 1845 SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028, 1846 SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029, 1847 SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a, 1848 SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b, 1849 SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c, 1850 SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d, 1851 SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e, 1852 SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f, 1853 SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030, 1854 SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031, 1855 SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032, 1856 SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033, 1857 SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034, 1858 SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035, 1859 SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036, 1860 SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037, 1861 SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038, 1862 SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039, 1863 SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a, 1864 SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b, 1865 SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c, 1866 SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d, 1867 SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e, 1868 SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f, 1869 SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040, 1870 SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041, 1871 SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042, 1872 SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043, 1873 SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044, 1874 SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045, 1875 SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046, 1876 SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047, 1877 SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048, 1878 SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049, 1879 SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a, 1880 SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b, 1881 SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c, 1882 SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d, 1883 SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e, 1884 SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f, 1885 SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050, 1886 SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051, 1887 SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052, 1888 SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053, 1889 SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054, 1890 SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055, 1891 SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056, 1892 SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057, 1893 SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058, 1894 SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059, 1895 SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a, 1896 SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b, 1897 SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c, 1898 SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d, 1899 SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e, 1900 SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f, 1901 SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060, 1902 SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061, 1903 SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062, 1904 SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063, 1905 SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064, 1906 SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065, 1907 SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066, 1908 SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067, 1909 SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068, 1910 SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069, 1911 SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a, 1912 SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b, 1913 SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c, 1914 SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d, 1915 SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e, 1916 SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f, 1917 SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070, 1918 SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071, 1919 SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072, 1920 SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073, 1921 SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074, 1922 SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075, 1923 SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076, 1924 SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077, 1925 SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078, 1926 SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079, 1927 SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a, 1928 SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b, 1929 SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c, 1930 SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d, 1931 SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e, 1932 SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f, 1933 SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080, 1934 SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081, 1935 SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082, 1936 SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083, 1937 SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084, 1938 SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085, 1939 SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086, 1940 SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087, 1941 SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088, 1942 SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089, 1943 SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a, 1944 SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b, 1945 SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c, 1946 SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d, 1947 SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e, 1948 SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f, 1949 SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090, 1950 SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091, 1951 SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092, 1952 SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093, 1953 SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094, 1954 SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095, 1955 SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096, 1956 SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097, 1957 SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098, 1958 SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099, 1959 SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a, 1960 SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b, 1961 SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c, 1962 SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d, 1963 SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e, 1964 SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f, 1965 SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0, 1966 SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1, 1967 SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2, 1968 SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3, 1969 SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4, 1970 SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5, 1971 SEM_PERF_SEL_MC_RD_REQ = 0x000000a6, 1972 SEM_PERF_SEL_MC_RD_RET = 0x000000a7, 1973 SEM_PERF_SEL_MC_WR_REQ = 0x000000a8, 1974 SEM_PERF_SEL_MC_WR_RET = 0x000000a9, 1975 SEM_PERF_SEL_ATC_REQ = 0x000000aa, 1976 SEM_PERF_SEL_ATC_RET = 0x000000ab, 1977 SEM_PERF_SEL_ATC_XNACK = 0x000000ac, 1978 SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad, 1979 } SEM_PERF_SEL; 1980 1981 /******************************************************* 1982 * SDMA Enums 1983 *******************************************************/ 1984 1985 /* 1986 * SDMA_PERF_SEL enum 1987 */ 1988 1989 typedef enum SDMA_PERF_SEL { 1990 SDMA_PERF_SEL_CYCLE = 0x00000000, 1991 SDMA_PERF_SEL_IDLE = 0x00000001, 1992 SDMA_PERF_SEL_REG_IDLE = 0x00000002, 1993 SDMA_PERF_SEL_RB_EMPTY = 0x00000003, 1994 SDMA_PERF_SEL_RB_FULL = 0x00000004, 1995 SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005, 1996 SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006, 1997 SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007, 1998 SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008, 1999 SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009, 2000 SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a, 2001 SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b, 2002 SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c, 2003 SDMA_PERF_SEL_EX_IDLE = 0x0000000d, 2004 SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e, 2005 SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f, 2006 SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010, 2007 SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011, 2008 SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012, 2009 SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013, 2010 SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014, 2011 SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015, 2012 SDMA_PERF_SEL_DRM_IDLE = 0x00000016, 2013 SDMA_PERF_SEL_DRM_REQ_STALL = 0x00000017, 2014 SDMA_PERF_SEL_SEM_IDLE = 0x00000018, 2015 SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019, 2016 SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a, 2017 SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b, 2018 SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c, 2019 SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d, 2020 SDMA_PERF_SEL_INT_IDLE = 0x0000001e, 2021 SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f, 2022 SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020, 2023 SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021, 2024 SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022, 2025 SDMA_PERF_SEL_NUM_PACKET = 0x00000023, 2026 SDMA_PERF_SEL_DRM1_REQ_STALL = 0x00000024, 2027 SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025, 2028 SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026, 2029 SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027, 2030 SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028, 2031 SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029, 2032 SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a, 2033 SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b, 2034 SDMA_PERF_SEL_CE_DRM_IDLE = 0x0000002c, 2035 SDMA_PERF_SEL_CE_DRM1_IDLE = 0x0000002d, 2036 SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e, 2037 SDMA_PERF_SEL_CE_DRM_FULL = 0x0000002f, 2038 SDMA_PERF_SEL_CE_DRM1_FULL = 0x00000030, 2039 SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031, 2040 SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032, 2041 SDMA_PERF_SEL_CE_RD_STALL = 0x00000033, 2042 SDMA_PERF_SEL_CE_WR_STALL = 0x00000034, 2043 SDMA_PERF_SEL_GFX_SELECT = 0x00000035, 2044 SDMA_PERF_SEL_RLC0_SELECT = 0x00000036, 2045 SDMA_PERF_SEL_RLC1_SELECT = 0x00000037, 2046 SDMA_PERF_SEL_PAGE_SELECT = 0x00000038, 2047 SDMA_PERF_SEL_CTX_CHANGE = 0x00000039, 2048 SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a, 2049 SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b, 2050 SDMA_PERF_SEL_DOORBELL = 0x0000003c, 2051 SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d, 2052 SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e, 2053 SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f, 2054 SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040, 2055 SDMA_PERF_SEL_CE_L1_STALL = 0x00000041, 2056 SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042, 2057 SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043, 2058 SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044, 2059 SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045, 2060 SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046, 2061 SDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047, 2062 SDMA_PERF_SEL_ATCL2_FREE = 0x00000048, 2063 SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049, 2064 SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a, 2065 SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b, 2066 SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c, 2067 SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d, 2068 SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e, 2069 SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f, 2070 SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050, 2071 SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051, 2072 SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052, 2073 SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053, 2074 SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054, 2075 SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055, 2076 SDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056, 2077 SDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057, 2078 SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058, 2079 SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059, 2080 SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a, 2081 SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b, 2082 SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c, 2083 SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d, 2084 SDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e, 2085 SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 0x000000fe, 2086 SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 0x000000ff, 2087 } SDMA_PERF_SEL; 2088 2089 /******************************************************* 2090 * SMUIO Enums 2091 *******************************************************/ 2092 2093 /* 2094 * ROM_SIGNATURE value 2095 */ 2096 2097 #define ROM_SIGNATURE 0x0000aa55 2098 2099 /******************************************************* 2100 * GDS Enums 2101 *******************************************************/ 2102 2103 /******************************************************* 2104 * CB Enums 2105 *******************************************************/ 2106 2107 /* 2108 * SurfaceNumber enum 2109 */ 2110 2111 typedef enum SurfaceNumber { 2112 NUMBER_UNORM = 0x00000000, 2113 NUMBER_SNORM = 0x00000001, 2114 NUMBER_USCALED = 0x00000002, 2115 NUMBER_SSCALED = 0x00000003, 2116 NUMBER_UINT = 0x00000004, 2117 NUMBER_SINT = 0x00000005, 2118 NUMBER_SRGB = 0x00000006, 2119 NUMBER_FLOAT = 0x00000007, 2120 } SurfaceNumber; 2121 2122 /* 2123 * SurfaceSwap enum 2124 */ 2125 2126 typedef enum SurfaceSwap { 2127 SWAP_STD = 0x00000000, 2128 SWAP_ALT = 0x00000001, 2129 SWAP_STD_REV = 0x00000002, 2130 SWAP_ALT_REV = 0x00000003, 2131 } SurfaceSwap; 2132 2133 /* 2134 * CBMode enum 2135 */ 2136 2137 typedef enum CBMode { 2138 CB_DISABLE = 0x00000000, 2139 CB_NORMAL = 0x00000001, 2140 CB_ELIMINATE_FAST_CLEAR = 0x00000002, 2141 CB_RESOLVE = 0x00000003, 2142 CB_DECOMPRESS = 0x00000004, 2143 CB_FMASK_DECOMPRESS = 0x00000005, 2144 CB_DCC_DECOMPRESS = 0x00000006, 2145 } CBMode; 2146 2147 /* 2148 * RoundMode enum 2149 */ 2150 2151 typedef enum RoundMode { 2152 ROUND_BY_HALF = 0x00000000, 2153 ROUND_TRUNCATE = 0x00000001, 2154 } RoundMode; 2155 2156 /* 2157 * SourceFormat enum 2158 */ 2159 2160 typedef enum SourceFormat { 2161 EXPORT_4C_32BPC = 0x00000000, 2162 EXPORT_4C_16BPC = 0x00000001, 2163 EXPORT_2C_32BPC_GR = 0x00000002, 2164 EXPORT_2C_32BPC_AR = 0x00000003, 2165 } SourceFormat; 2166 2167 /* 2168 * BlendOp enum 2169 */ 2170 2171 typedef enum BlendOp { 2172 BLEND_ZERO = 0x00000000, 2173 BLEND_ONE = 0x00000001, 2174 BLEND_SRC_COLOR = 0x00000002, 2175 BLEND_ONE_MINUS_SRC_COLOR = 0x00000003, 2176 BLEND_SRC_ALPHA = 0x00000004, 2177 BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005, 2178 BLEND_DST_ALPHA = 0x00000006, 2179 BLEND_ONE_MINUS_DST_ALPHA = 0x00000007, 2180 BLEND_DST_COLOR = 0x00000008, 2181 BLEND_ONE_MINUS_DST_COLOR = 0x00000009, 2182 BLEND_SRC_ALPHA_SATURATE = 0x0000000a, 2183 BLEND_BOTH_SRC_ALPHA = 0x0000000b, 2184 BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c, 2185 BLEND_CONSTANT_COLOR = 0x0000000d, 2186 BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e, 2187 BLEND_SRC1_COLOR = 0x0000000f, 2188 BLEND_INV_SRC1_COLOR = 0x00000010, 2189 BLEND_SRC1_ALPHA = 0x00000011, 2190 BLEND_INV_SRC1_ALPHA = 0x00000012, 2191 BLEND_CONSTANT_ALPHA = 0x00000013, 2192 BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014, 2193 } BlendOp; 2194 2195 /* 2196 * CombFunc enum 2197 */ 2198 2199 typedef enum CombFunc { 2200 COMB_DST_PLUS_SRC = 0x00000000, 2201 COMB_SRC_MINUS_DST = 0x00000001, 2202 COMB_MIN_DST_SRC = 0x00000002, 2203 COMB_MAX_DST_SRC = 0x00000003, 2204 COMB_DST_MINUS_SRC = 0x00000004, 2205 } CombFunc; 2206 2207 /* 2208 * BlendOpt enum 2209 */ 2210 2211 typedef enum BlendOpt { 2212 FORCE_OPT_AUTO = 0x00000000, 2213 FORCE_OPT_DISABLE = 0x00000001, 2214 FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002, 2215 FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003, 2216 FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004, 2217 FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005, 2218 FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006, 2219 FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007, 2220 } BlendOpt; 2221 2222 /* 2223 * CmaskCode enum 2224 */ 2225 2226 typedef enum CmaskCode { 2227 CMASK_CLR00_F0 = 0x00000000, 2228 CMASK_CLR00_F1 = 0x00000001, 2229 CMASK_CLR00_F2 = 0x00000002, 2230 CMASK_CLR00_FX = 0x00000003, 2231 CMASK_CLR01_F0 = 0x00000004, 2232 CMASK_CLR01_F1 = 0x00000005, 2233 CMASK_CLR01_F2 = 0x00000006, 2234 CMASK_CLR01_FX = 0x00000007, 2235 CMASK_CLR10_F0 = 0x00000008, 2236 CMASK_CLR10_F1 = 0x00000009, 2237 CMASK_CLR10_F2 = 0x0000000a, 2238 CMASK_CLR10_FX = 0x0000000b, 2239 CMASK_CLR11_F0 = 0x0000000c, 2240 CMASK_CLR11_F1 = 0x0000000d, 2241 CMASK_CLR11_F2 = 0x0000000e, 2242 CMASK_CLR11_FX = 0x0000000f, 2243 } CmaskCode; 2244 2245 /* 2246 * CmaskAddr enum 2247 */ 2248 2249 typedef enum CmaskAddr { 2250 CMASK_ADDR_TILED = 0x00000000, 2251 CMASK_ADDR_LINEAR = 0x00000001, 2252 CMASK_ADDR_COMPATIBLE = 0x00000002, 2253 } CmaskAddr; 2254 2255 /* 2256 * MemArbMode enum 2257 */ 2258 2259 typedef enum MemArbMode { 2260 MEM_ARB_MODE_FIXED = 0x00000000, 2261 MEM_ARB_MODE_AGE = 0x00000001, 2262 MEM_ARB_MODE_WEIGHT = 0x00000002, 2263 MEM_ARB_MODE_BOTH = 0x00000003, 2264 } MemArbMode; 2265 2266 /* 2267 * CBPerfSel enum 2268 */ 2269 2270 typedef enum CBPerfSel { 2271 CB_PERF_SEL_NONE = 0x00000000, 2272 CB_PERF_SEL_BUSY = 0x00000001, 2273 CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002, 2274 CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003, 2275 CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004, 2276 CB_PERF_SEL_DRAWN_QUAD = 0x00000005, 2277 CB_PERF_SEL_DRAWN_PIXEL = 0x00000006, 2278 CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007, 2279 CB_PERF_SEL_DRAWN_TILE = 0x00000008, 2280 CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009, 2281 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a, 2282 CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b, 2283 CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c, 2284 CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d, 2285 CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e, 2286 CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f, 2287 CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010, 2288 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011, 2289 CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012, 2290 CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013, 2291 CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014, 2292 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015, 2293 CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016, 2294 CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017, 2295 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018, 2296 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019, 2297 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a, 2298 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b, 2299 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c, 2300 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d, 2301 CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e, 2302 CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f, 2303 CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020, 2304 CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021, 2305 CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022, 2306 CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023, 2307 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024, 2308 CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025, 2309 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026, 2310 CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027, 2311 CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028, 2312 CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029, 2313 CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a, 2314 CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b, 2315 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c, 2316 CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d, 2317 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e, 2318 CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f, 2319 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030, 2320 CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031, 2321 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032, 2322 CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033, 2323 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034, 2324 CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035, 2325 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036, 2326 CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037, 2327 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038, 2328 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039, 2329 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a, 2330 CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b, 2331 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c, 2332 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d, 2333 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e, 2334 CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f, 2335 CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040, 2336 CB_PERF_SEL_CM_CACHE_HIT = 0x00000041, 2337 CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042, 2338 CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043, 2339 CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044, 2340 CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045, 2341 CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046, 2342 CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047, 2343 CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048, 2344 CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049, 2345 CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a, 2346 CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b, 2347 CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c, 2348 CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d, 2349 CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e, 2350 CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f, 2351 CB_PERF_SEL_FC_CACHE_HIT = 0x00000050, 2352 CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051, 2353 CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052, 2354 CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053, 2355 CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054, 2356 CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055, 2357 CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056, 2358 CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057, 2359 CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058, 2360 CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059, 2361 CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a, 2362 CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b, 2363 CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c, 2364 CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d, 2365 CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e, 2366 CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f, 2367 CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060, 2368 CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061, 2369 CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062, 2370 CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063, 2371 CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064, 2372 CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065, 2373 CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066, 2374 CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067, 2375 CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068, 2376 CB_PERF_SEL_CC_CACHE_STALL = 0x00000069, 2377 CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a, 2378 CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b, 2379 CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c, 2380 CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d, 2381 CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e, 2382 CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x0000006f, 2383 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x00000070, 2384 CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x00000071, 2385 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x00000072, 2386 CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x00000073, 2387 CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x00000074, 2388 CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x00000075, 2389 CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x00000076, 2390 CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000077, 2391 CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000078, 2392 CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000079, 2393 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x0000007a, 2394 CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x0000007b, 2395 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x0000007c, 2396 CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x0000007d, 2397 CB_PERF_SEL_CM_MC_READ_REQUEST = 0x0000007e, 2398 CB_PERF_SEL_FC_MC_READ_REQUEST = 0x0000007f, 2399 CB_PERF_SEL_CC_MC_READ_REQUEST = 0x00000080, 2400 CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x00000081, 2401 CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000082, 2402 CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000083, 2403 CB_PERF_SEL_CM_TQ_FULL = 0x00000084, 2404 CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x00000085, 2405 CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x00000086, 2406 CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x00000087, 2407 CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000088, 2408 CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x00000089, 2409 CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x0000008a, 2410 CB_PERF_SEL_CC_SF_FULL = 0x0000008b, 2411 CB_PERF_SEL_CC_RB_FULL = 0x0000008c, 2412 CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x0000008d, 2413 CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x0000008e, 2414 CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x0000008f, 2415 CB_PERF_SEL_EVENT = 0x00000090, 2416 CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000091, 2417 CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000092, 2418 CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000093, 2419 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000094, 2420 CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x00000095, 2421 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000096, 2422 CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000097, 2423 CB_PERF_SEL_CC_SURFACE_SYNC = 0x00000098, 2424 CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x00000099, 2425 CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x0000009a, 2426 CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x0000009b, 2427 CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x0000009c, 2428 CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x0000009d, 2429 CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x0000009e, 2430 CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x0000009f, 2431 CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x000000a0, 2432 CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0x000000a1, 2433 CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x000000a2, 2434 CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x000000a3, 2435 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x000000a4, 2436 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x000000a5, 2437 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x000000a6, 2438 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x000000a7, 2439 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x000000a8, 2440 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x000000a9, 2441 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x000000aa, 2442 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x000000ab, 2443 CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0x000000ac, 2444 CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x000000ad, 2445 CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x000000ae, 2446 CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x000000af, 2447 CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x000000b0, 2448 CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x000000b1, 2449 CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x000000b2, 2450 CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x000000b3, 2451 CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0x000000b4, 2452 CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0x000000b5, 2453 CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0x000000b6, 2454 CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0x000000b7, 2455 CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0x000000b8, 2456 CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0x000000b9, 2457 CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0x000000ba, 2458 CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0x000000bb, 2459 CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0x000000bc, 2460 CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0x000000bd, 2461 CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0x000000be, 2462 CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0x000000bf, 2463 CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0x000000c0, 2464 CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0x000000c1, 2465 CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0x000000c2, 2466 CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0x000000c3, 2467 CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0x000000c4, 2468 CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0x000000c5, 2469 CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0x000000c6, 2470 CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0x000000c7, 2471 CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0x000000c8, 2472 CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0x000000c9, 2473 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0x000000ca, 2474 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0x000000cb, 2475 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0x000000cc, 2476 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0x000000cd, 2477 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0x000000ce, 2478 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0x000000cf, 2479 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0x000000d0, 2480 CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0x000000d1, 2481 CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0x000000d2, 2482 CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0x000000d3, 2483 CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0x000000d4, 2484 CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000d5, 2485 CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000d6, 2486 CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000d7, 2487 CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000d8, 2488 CB_PERF_SEL_DRAWN_BUSY = 0x000000d9, 2489 CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0x000000da, 2490 CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0x000000db, 2491 CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0x000000dc, 2492 CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0x000000dd, 2493 CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 0x000000de, 2494 CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0x000000df, 2495 CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0x000000e0, 2496 CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0x000000e1, 2497 CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 0x000000e2, 2498 CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0x000000e3, 2499 CB_PERF_SEL_FC_DOC_IS_STALLED = 0x000000e4, 2500 CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0x000000e5, 2501 CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0x000000e6, 2502 CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0x000000e7, 2503 CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0x000000e8, 2504 CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0x000000e9, 2505 CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0x000000ea, 2506 CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0x000000eb, 2507 CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0x000000ec, 2508 CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0x000000ed, 2509 CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0x000000ee, 2510 CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0x000000ef, 2511 CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0x000000f0, 2512 CB_PERF_SEL_FC_DCC_CACHE_HIT = 0x000000f1, 2513 CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0x000000f2, 2514 CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0x000000f3, 2515 CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0x000000f4, 2516 CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x000000f5, 2517 CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x000000f6, 2518 CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x000000f7, 2519 CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0x000000f8, 2520 CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0x000000f9, 2521 CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0x000000fa, 2522 CB_PERF_SEL_FC_DCC_CACHE_STALL = 0x000000fb, 2523 CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0x000000fc, 2524 CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0x000000fd, 2525 CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0x000000fe, 2526 CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000ff, 2527 CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x00000100, 2528 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x00000101, 2529 CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x00000102, 2530 CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x00000103, 2531 CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x00000104, 2532 CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x00000105, 2533 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x00000106, 2534 CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x00000107, 2535 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x00000108, 2536 CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x00000109, 2537 CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x0000010a, 2538 CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x0000010b, 2539 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 0x0000010c, 2540 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000010d, 2541 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 0x0000010e, 2542 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 0x0000010f, 2543 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 0x00000110, 2544 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000111, 2545 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000112, 2546 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000113, 2547 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 0x00000114, 2548 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 0x00000115, 2549 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 0x00000116, 2550 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 0x00000117, 2551 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000118, 2552 CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000119, 2553 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x0000011a, 2554 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 0x0000011b, 2555 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 0x0000011c, 2556 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 0x0000011d, 2557 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 0x0000011e, 2558 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x0000011f, 2559 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 0x00000120, 2560 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 0x00000121, 2561 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 0x00000122, 2562 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 0x00000123, 2563 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x00000124, 2564 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 0x00000125, 2565 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 0x00000126, 2566 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 0x00000127, 2567 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 0x00000128, 2568 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 0x00000129, 2569 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 0x0000012a, 2570 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 0x0000012b, 2571 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 0x0000012c, 2572 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 0x0000012d, 2573 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 0x0000012e, 2574 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 0x0000012f, 2575 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 0x00000130, 2576 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 0x00000131, 2577 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 0x00000132, 2578 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 0x00000133, 2579 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 0x00000134, 2580 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 0x00000135, 2581 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 0x00000136, 2582 CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 0x00000137, 2583 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 0x00000138, 2584 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 0x00000139, 2585 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013a, 2586 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013b, 2587 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 0x0000013c, 2588 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 0x0000013d, 2589 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 0x0000013e, 2590 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 0x0000013f, 2591 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000140, 2592 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000141, 2593 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000142, 2594 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 0x00000143, 2595 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000144, 2596 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000145, 2597 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000146, 2598 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 0x00000147, 2599 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 0x00000148, 2600 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 0x00000149, 2601 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 0x0000014a, 2602 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 0x0000014b, 2603 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 0x0000014c, 2604 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 0x0000014d, 2605 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014e, 2606 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000014f, 2607 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000150, 2608 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000151, 2609 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000152, 2610 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000153, 2611 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000154, 2612 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000155, 2613 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 0x00000156, 2614 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 0x00000157, 2615 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 0x00000158, 2616 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 0x00000159, 2617 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 0x0000015a, 2618 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 0x0000015b, 2619 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x0000015c, 2620 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x0000015d, 2621 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 0x0000015e, 2622 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 0x0000015f, 2623 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 0x00000160, 2624 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 0x00000161, 2625 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 0x00000162, 2626 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x00000163, 2627 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x00000164, 2628 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 0x00000165, 2629 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 0x00000166, 2630 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 0x00000167, 2631 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 0x00000168, 2632 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 0x00000169, 2633 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 0x0000016a, 2634 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x0000016b, 2635 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x0000016c, 2636 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 0x0000016d, 2637 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 0x0000016e, 2638 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 0x0000016f, 2639 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 0x00000170, 2640 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 0x00000171, 2641 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x00000172, 2642 CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x00000173, 2643 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x00000174, 2644 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x00000175, 2645 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x00000176, 2646 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x00000177, 2647 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x00000178, 2648 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x00000179, 2649 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x0000017a, 2650 CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x0000017b, 2651 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x0000017c, 2652 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x0000017d, 2653 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x0000017e, 2654 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x0000017f, 2655 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x00000180, 2656 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x00000181, 2657 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x00000182, 2658 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x00000183, 2659 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x00000184, 2660 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x00000185, 2661 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x00000186, 2662 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x00000187, 2663 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x00000188, 2664 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x00000189, 2665 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x0000018a, 2666 CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x0000018b, 2667 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x0000018c, 2668 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x0000018d, 2669 CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x0000018e, 2670 CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x0000018f, 2671 CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x00000190, 2672 CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x00000191, 2673 CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x00000192, 2674 CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x00000193, 2675 CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x00000194, 2676 } CBPerfSel; 2677 2678 /* 2679 * CBPerfOpFilterSel enum 2680 */ 2681 2682 typedef enum CBPerfOpFilterSel { 2683 CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000, 2684 CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001, 2685 CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002, 2686 CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003, 2687 CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004, 2688 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005, 2689 } CBPerfOpFilterSel; 2690 2691 /* 2692 * CBPerfClearFilterSel enum 2693 */ 2694 2695 typedef enum CBPerfClearFilterSel { 2696 CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000, 2697 CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001, 2698 } CBPerfClearFilterSel; 2699 2700 /******************************************************* 2701 * TC Enums 2702 *******************************************************/ 2703 2704 /* 2705 * TC_OP_MASKS enum 2706 */ 2707 2708 typedef enum TC_OP_MASKS { 2709 TC_OP_MASK_FLUSH_DENROM = 0x00000008, 2710 TC_OP_MASK_64 = 0x00000020, 2711 TC_OP_MASK_NO_RTN = 0x00000040, 2712 } TC_OP_MASKS; 2713 2714 /* 2715 * TC_OP enum 2716 */ 2717 2718 typedef enum TC_OP { 2719 TC_OP_READ = 0x00000000, 2720 TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001, 2721 TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002, 2722 TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003, 2723 TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004, 2724 TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005, 2725 TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006, 2726 TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007, 2727 TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008, 2728 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009, 2729 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a, 2730 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b, 2731 TC_OP_PROBE_FILTER = 0x0000000c, 2732 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d, 2733 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e, 2734 TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f, 2735 TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010, 2736 TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011, 2737 TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012, 2738 TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013, 2739 TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014, 2740 TC_OP_ATOMIC_AND_RTN_32 = 0x00000015, 2741 TC_OP_ATOMIC_OR_RTN_32 = 0x00000016, 2742 TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017, 2743 TC_OP_ATOMIC_INC_RTN_32 = 0x00000018, 2744 TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019, 2745 TC_OP_WBINVL1_VOL = 0x0000001a, 2746 TC_OP_WBINVL1_SD = 0x0000001b, 2747 TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c, 2748 TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d, 2749 TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e, 2750 TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f, 2751 TC_OP_WRITE = 0x00000020, 2752 TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021, 2753 TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022, 2754 TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023, 2755 TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024, 2756 TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025, 2757 TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026, 2758 TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027, 2759 TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028, 2760 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029, 2761 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a, 2762 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b, 2763 TC_OP_WBINVL2_SD = 0x0000002c, 2764 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d, 2765 TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e, 2766 TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f, 2767 TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030, 2768 TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031, 2769 TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032, 2770 TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033, 2771 TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034, 2772 TC_OP_ATOMIC_AND_RTN_64 = 0x00000035, 2773 TC_OP_ATOMIC_OR_RTN_64 = 0x00000036, 2774 TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037, 2775 TC_OP_ATOMIC_INC_RTN_64 = 0x00000038, 2776 TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039, 2777 TC_OP_WBL2_NC = 0x0000003a, 2778 TC_OP_WBL2_WC = 0x0000003b, 2779 TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c, 2780 TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d, 2781 TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e, 2782 TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f, 2783 TC_OP_WBINVL1 = 0x00000040, 2784 TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041, 2785 TC_OP_ATOMIC_FMIN_32 = 0x00000042, 2786 TC_OP_ATOMIC_FMAX_32 = 0x00000043, 2787 TC_OP_RESERVED_FOP_32_0 = 0x00000044, 2788 TC_OP_RESERVED_FOP_32_1 = 0x00000045, 2789 TC_OP_RESERVED_FOP_32_2 = 0x00000046, 2790 TC_OP_ATOMIC_SWAP_32 = 0x00000047, 2791 TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048, 2792 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049, 2793 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a, 2794 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b, 2795 TC_OP_INV_METADATA = 0x0000004c, 2796 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d, 2797 TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e, 2798 TC_OP_ATOMIC_ADD_32 = 0x0000004f, 2799 TC_OP_ATOMIC_SUB_32 = 0x00000050, 2800 TC_OP_ATOMIC_SMIN_32 = 0x00000051, 2801 TC_OP_ATOMIC_UMIN_32 = 0x00000052, 2802 TC_OP_ATOMIC_SMAX_32 = 0x00000053, 2803 TC_OP_ATOMIC_UMAX_32 = 0x00000054, 2804 TC_OP_ATOMIC_AND_32 = 0x00000055, 2805 TC_OP_ATOMIC_OR_32 = 0x00000056, 2806 TC_OP_ATOMIC_XOR_32 = 0x00000057, 2807 TC_OP_ATOMIC_INC_32 = 0x00000058, 2808 TC_OP_ATOMIC_DEC_32 = 0x00000059, 2809 TC_OP_INVL2_NC = 0x0000005a, 2810 TC_OP_NOP_RTN0 = 0x0000005b, 2811 TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c, 2812 TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d, 2813 TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e, 2814 TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f, 2815 TC_OP_WBINVL2 = 0x00000060, 2816 TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061, 2817 TC_OP_ATOMIC_FMIN_64 = 0x00000062, 2818 TC_OP_ATOMIC_FMAX_64 = 0x00000063, 2819 TC_OP_RESERVED_FOP_64_0 = 0x00000064, 2820 TC_OP_RESERVED_FOP_64_1 = 0x00000065, 2821 TC_OP_RESERVED_FOP_64_2 = 0x00000066, 2822 TC_OP_ATOMIC_SWAP_64 = 0x00000067, 2823 TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068, 2824 TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069, 2825 TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a, 2826 TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b, 2827 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c, 2828 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d, 2829 TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e, 2830 TC_OP_ATOMIC_ADD_64 = 0x0000006f, 2831 TC_OP_ATOMIC_SUB_64 = 0x00000070, 2832 TC_OP_ATOMIC_SMIN_64 = 0x00000071, 2833 TC_OP_ATOMIC_UMIN_64 = 0x00000072, 2834 TC_OP_ATOMIC_SMAX_64 = 0x00000073, 2835 TC_OP_ATOMIC_UMAX_64 = 0x00000074, 2836 TC_OP_ATOMIC_AND_64 = 0x00000075, 2837 TC_OP_ATOMIC_OR_64 = 0x00000076, 2838 TC_OP_ATOMIC_XOR_64 = 0x00000077, 2839 TC_OP_ATOMIC_INC_64 = 0x00000078, 2840 TC_OP_ATOMIC_DEC_64 = 0x00000079, 2841 TC_OP_WBINVL2_NC = 0x0000007a, 2842 TC_OP_NOP_ACK = 0x0000007b, 2843 TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c, 2844 TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d, 2845 TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e, 2846 TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f, 2847 } TC_OP; 2848 2849 /* 2850 * TC_CHUB_REQ_CREDITS_ENUM enum 2851 */ 2852 2853 typedef enum TC_CHUB_REQ_CREDITS_ENUM { 2854 TC_CHUB_REQ_CREDITS = 0x00000010, 2855 } TC_CHUB_REQ_CREDITS_ENUM; 2856 2857 /* 2858 * CHUB_TC_RET_CREDITS_ENUM enum 2859 */ 2860 2861 typedef enum CHUB_TC_RET_CREDITS_ENUM { 2862 CHUB_TC_RET_CREDITS = 0x00000020, 2863 } CHUB_TC_RET_CREDITS_ENUM; 2864 2865 /* 2866 * TC_NACKS enum 2867 */ 2868 2869 typedef enum TC_NACKS { 2870 TC_NACK_NO_FAULT = 0x00000000, 2871 TC_NACK_PAGE_FAULT = 0x00000001, 2872 TC_NACK_PROTECTION_FAULT = 0x00000002, 2873 TC_NACK_DATA_ERROR = 0x00000003, 2874 } TC_NACKS; 2875 2876 /* 2877 * TC_EA_CID enum 2878 */ 2879 2880 typedef enum TC_EA_CID { 2881 TC_EA_CID_RT = 0x00000000, 2882 TC_EA_CID_FMASK = 0x00000001, 2883 TC_EA_CID_DCC = 0x00000002, 2884 TC_EA_CID_TCPMETA = 0x00000003, 2885 TC_EA_CID_Z = 0x00000004, 2886 TC_EA_CID_STENCIL = 0x00000005, 2887 TC_EA_CID_HTILE = 0x00000006, 2888 TC_EA_CID_MISC = 0x00000007, 2889 TC_EA_CID_TCP = 0x00000008, 2890 TC_EA_CID_SQC = 0x00000009, 2891 TC_EA_CID_CPF = 0x0000000a, 2892 TC_EA_CID_CPG = 0x0000000b, 2893 TC_EA_CID_IA = 0x0000000c, 2894 TC_EA_CID_WD = 0x0000000d, 2895 TC_EA_CID_PA = 0x0000000e, 2896 TC_EA_CID_UTCL2_TPI = 0x0000000f, 2897 } TC_EA_CID; 2898 2899 /******************************************************* 2900 * GC_CAC Enums 2901 *******************************************************/ 2902 2903 /******************************************************* 2904 * RLC Enums 2905 *******************************************************/ 2906 2907 /******************************************************* 2908 * SPI Enums 2909 *******************************************************/ 2910 2911 /* 2912 * SPI_SAMPLE_CNTL enum 2913 */ 2914 2915 typedef enum SPI_SAMPLE_CNTL { 2916 CENTROIDS_ONLY = 0x00000000, 2917 CENTERS_ONLY = 0x00000001, 2918 CENTROIDS_AND_CENTERS = 0x00000002, 2919 UNDEF = 0x00000003, 2920 } SPI_SAMPLE_CNTL; 2921 2922 /* 2923 * SPI_FOG_MODE enum 2924 */ 2925 2926 typedef enum SPI_FOG_MODE { 2927 SPI_FOG_NONE = 0x00000000, 2928 SPI_FOG_EXP = 0x00000001, 2929 SPI_FOG_EXP2 = 0x00000002, 2930 SPI_FOG_LINEAR = 0x00000003, 2931 } SPI_FOG_MODE; 2932 2933 /* 2934 * SPI_PNT_SPRITE_OVERRIDE enum 2935 */ 2936 2937 typedef enum SPI_PNT_SPRITE_OVERRIDE { 2938 SPI_PNT_SPRITE_SEL_0 = 0x00000000, 2939 SPI_PNT_SPRITE_SEL_1 = 0x00000001, 2940 SPI_PNT_SPRITE_SEL_S = 0x00000002, 2941 SPI_PNT_SPRITE_SEL_T = 0x00000003, 2942 SPI_PNT_SPRITE_SEL_NONE = 0x00000004, 2943 } SPI_PNT_SPRITE_OVERRIDE; 2944 2945 /* 2946 * SPI_PERFCNT_SEL enum 2947 */ 2948 2949 typedef enum SPI_PERFCNT_SEL { 2950 SPI_PERF_VS_WINDOW_VALID = 0x00000000, 2951 SPI_PERF_VS_BUSY = 0x00000001, 2952 SPI_PERF_VS_FIRST_WAVE = 0x00000002, 2953 SPI_PERF_VS_LAST_WAVE = 0x00000003, 2954 SPI_PERF_VS_LSHS_DEALLOC = 0x00000004, 2955 SPI_PERF_VS_PC_STALL = 0x00000005, 2956 SPI_PERF_VS_POS0_STALL = 0x00000006, 2957 SPI_PERF_VS_POS1_STALL = 0x00000007, 2958 SPI_PERF_VS_CRAWLER_STALL = 0x00000008, 2959 SPI_PERF_VS_EVENT_WAVE = 0x00000009, 2960 SPI_PERF_VS_WAVE = 0x0000000a, 2961 SPI_PERF_VS_PERS_UPD_FULL0 = 0x0000000b, 2962 SPI_PERF_VS_PERS_UPD_FULL1 = 0x0000000c, 2963 SPI_PERF_VS_LATE_ALLOC_FULL = 0x0000000d, 2964 SPI_PERF_VS_FIRST_SUBGRP = 0x0000000e, 2965 SPI_PERF_VS_LAST_SUBGRP = 0x0000000f, 2966 SPI_PERF_GS_WINDOW_VALID = 0x00000010, 2967 SPI_PERF_GS_BUSY = 0x00000011, 2968 SPI_PERF_GS_CRAWLER_STALL = 0x00000012, 2969 SPI_PERF_GS_EVENT_WAVE = 0x00000013, 2970 SPI_PERF_GS_WAVE = 0x00000014, 2971 SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000015, 2972 SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000016, 2973 SPI_PERF_GS_FIRST_SUBGRP = 0x00000017, 2974 SPI_PERF_GS_LAST_SUBGRP = 0x00000018, 2975 SPI_PERF_ES_WINDOW_VALID = 0x00000019, 2976 SPI_PERF_ES_BUSY = 0x0000001a, 2977 SPI_PERF_ES_CRAWLER_STALL = 0x0000001b, 2978 SPI_PERF_ES_FIRST_WAVE = 0x0000001c, 2979 SPI_PERF_ES_LAST_WAVE = 0x0000001d, 2980 SPI_PERF_ES_LSHS_DEALLOC = 0x0000001e, 2981 SPI_PERF_ES_EVENT_WAVE = 0x0000001f, 2982 SPI_PERF_ES_WAVE = 0x00000020, 2983 SPI_PERF_ES_PERS_UPD_FULL0 = 0x00000021, 2984 SPI_PERF_ES_PERS_UPD_FULL1 = 0x00000022, 2985 SPI_PERF_ES_FIRST_SUBGRP = 0x00000023, 2986 SPI_PERF_ES_LAST_SUBGRP = 0x00000024, 2987 SPI_PERF_HS_WINDOW_VALID = 0x00000025, 2988 SPI_PERF_HS_BUSY = 0x00000026, 2989 SPI_PERF_HS_CRAWLER_STALL = 0x00000027, 2990 SPI_PERF_HS_FIRST_WAVE = 0x00000028, 2991 SPI_PERF_HS_LAST_WAVE = 0x00000029, 2992 SPI_PERF_HS_LSHS_DEALLOC = 0x0000002a, 2993 SPI_PERF_HS_EVENT_WAVE = 0x0000002b, 2994 SPI_PERF_HS_WAVE = 0x0000002c, 2995 SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000002d, 2996 SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000002e, 2997 SPI_PERF_LS_WINDOW_VALID = 0x0000002f, 2998 SPI_PERF_LS_BUSY = 0x00000030, 2999 SPI_PERF_LS_CRAWLER_STALL = 0x00000031, 3000 SPI_PERF_LS_FIRST_WAVE = 0x00000032, 3001 SPI_PERF_LS_LAST_WAVE = 0x00000033, 3002 SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x00000034, 3003 SPI_PERF_LS_EVENT_WAVE = 0x00000035, 3004 SPI_PERF_LS_WAVE = 0x00000036, 3005 SPI_PERF_LS_PERS_UPD_FULL0 = 0x00000037, 3006 SPI_PERF_LS_PERS_UPD_FULL1 = 0x00000038, 3007 SPI_PERF_CSG_WINDOW_VALID = 0x00000039, 3008 SPI_PERF_CSG_BUSY = 0x0000003a, 3009 SPI_PERF_CSG_NUM_THREADGROUPS = 0x0000003b, 3010 SPI_PERF_CSG_CRAWLER_STALL = 0x0000003c, 3011 SPI_PERF_CSG_EVENT_WAVE = 0x0000003d, 3012 SPI_PERF_CSG_WAVE = 0x0000003e, 3013 SPI_PERF_CSN_WINDOW_VALID = 0x0000003f, 3014 SPI_PERF_CSN_BUSY = 0x00000040, 3015 SPI_PERF_CSN_NUM_THREADGROUPS = 0x00000041, 3016 SPI_PERF_CSN_CRAWLER_STALL = 0x00000042, 3017 SPI_PERF_CSN_EVENT_WAVE = 0x00000043, 3018 SPI_PERF_CSN_WAVE = 0x00000044, 3019 SPI_PERF_PS_CTL_WINDOW_VALID = 0x00000045, 3020 SPI_PERF_PS_CTL_BUSY = 0x00000046, 3021 SPI_PERF_PS_CTL_ACTIVE = 0x00000047, 3022 SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x00000048, 3023 SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x00000049, 3024 SPI_PERF_PS_CTL_EVENT_WAVE = 0x0000004a, 3025 SPI_PERF_PS_CTL_WAVE = 0x0000004b, 3026 SPI_PERF_PS_CTL_OPT_WAVE = 0x0000004c, 3027 SPI_PERF_PS_CTL_PASS_BIN0 = 0x0000004d, 3028 SPI_PERF_PS_CTL_PASS_BIN1 = 0x0000004e, 3029 SPI_PERF_PS_CTL_FPOS_BIN2 = 0x0000004f, 3030 SPI_PERF_PS_CTL_PRIM_BIN0 = 0x00000050, 3031 SPI_PERF_PS_CTL_PRIM_BIN1 = 0x00000051, 3032 SPI_PERF_PS_CTL_CNF_BIN2 = 0x00000052, 3033 SPI_PERF_PS_CTL_CNF_BIN3 = 0x00000053, 3034 SPI_PERF_PS_CTL_CRAWLER_STALL = 0x00000054, 3035 SPI_PERF_PS_CTL_LDS_RES_FULL = 0x00000055, 3036 SPI_PERF_PS_PERS_UPD_FULL0 = 0x00000056, 3037 SPI_PERF_PS_PERS_UPD_FULL1 = 0x00000057, 3038 SPI_PERF_PIX_ALLOC_PEND_CNT = 0x00000058, 3039 SPI_PERF_PIX_ALLOC_SCB_STALL = 0x00000059, 3040 SPI_PERF_PIX_ALLOC_DB0_STALL = 0x0000005a, 3041 SPI_PERF_PIX_ALLOC_DB1_STALL = 0x0000005b, 3042 SPI_PERF_PIX_ALLOC_DB2_STALL = 0x0000005c, 3043 SPI_PERF_PIX_ALLOC_DB3_STALL = 0x0000005d, 3044 SPI_PERF_LDS0_PC_VALID = 0x0000005e, 3045 SPI_PERF_LDS1_PC_VALID = 0x0000005f, 3046 SPI_PERF_RA_PIPE_REQ_BIN2 = 0x00000060, 3047 SPI_PERF_RA_TASK_REQ_BIN3 = 0x00000061, 3048 SPI_PERF_RA_WR_CTL_FULL = 0x00000062, 3049 SPI_PERF_RA_REQ_NO_ALLOC = 0x00000063, 3050 SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000064, 3051 SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x00000065, 3052 SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000066, 3053 SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x00000067, 3054 SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000068, 3055 SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x00000069, 3056 SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x0000006a, 3057 SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x0000006b, 3058 SPI_PERF_RA_RES_STALL_PS = 0x0000006c, 3059 SPI_PERF_RA_RES_STALL_VS = 0x0000006d, 3060 SPI_PERF_RA_RES_STALL_GS = 0x0000006e, 3061 SPI_PERF_RA_RES_STALL_ES = 0x0000006f, 3062 SPI_PERF_RA_RES_STALL_HS = 0x00000070, 3063 SPI_PERF_RA_RES_STALL_LS = 0x00000071, 3064 SPI_PERF_RA_RES_STALL_CSG = 0x00000072, 3065 SPI_PERF_RA_RES_STALL_CSN = 0x00000073, 3066 SPI_PERF_RA_TMP_STALL_PS = 0x00000074, 3067 SPI_PERF_RA_TMP_STALL_VS = 0x00000075, 3068 SPI_PERF_RA_TMP_STALL_GS = 0x00000076, 3069 SPI_PERF_RA_TMP_STALL_ES = 0x00000077, 3070 SPI_PERF_RA_TMP_STALL_HS = 0x00000078, 3071 SPI_PERF_RA_TMP_STALL_LS = 0x00000079, 3072 SPI_PERF_RA_TMP_STALL_CSG = 0x0000007a, 3073 SPI_PERF_RA_TMP_STALL_CSN = 0x0000007b, 3074 SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x0000007c, 3075 SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x0000007d, 3076 SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x0000007e, 3077 SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x0000007f, 3078 SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x00000080, 3079 SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x00000081, 3080 SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x00000082, 3081 SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x00000083, 3082 SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x00000084, 3083 SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x00000085, 3084 SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x00000086, 3085 SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x00000087, 3086 SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x00000088, 3087 SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x00000089, 3088 SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x0000008a, 3089 SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x0000008b, 3090 SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x0000008c, 3091 SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x0000008d, 3092 SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x0000008e, 3093 SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x0000008f, 3094 SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x00000090, 3095 SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x00000091, 3096 SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x00000092, 3097 SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x00000093, 3098 SPI_PERF_RA_LDS_CU_FULL_PS = 0x00000094, 3099 SPI_PERF_RA_LDS_CU_FULL_LS = 0x00000095, 3100 SPI_PERF_RA_LDS_CU_FULL_ES = 0x00000096, 3101 SPI_PERF_RA_LDS_CU_FULL_CSG = 0x00000097, 3102 SPI_PERF_RA_LDS_CU_FULL_CSN = 0x00000098, 3103 SPI_PERF_RA_BAR_CU_FULL_HS = 0x00000099, 3104 SPI_PERF_RA_BAR_CU_FULL_CSG = 0x0000009a, 3105 SPI_PERF_RA_BAR_CU_FULL_CSN = 0x0000009b, 3106 SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x0000009c, 3107 SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x0000009d, 3108 SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x0000009e, 3109 SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x0000009f, 3110 SPI_PERF_RA_WVLIM_STALL_PS = 0x000000a0, 3111 SPI_PERF_RA_WVLIM_STALL_VS = 0x000000a1, 3112 SPI_PERF_RA_WVLIM_STALL_GS = 0x000000a2, 3113 SPI_PERF_RA_WVLIM_STALL_ES = 0x000000a3, 3114 SPI_PERF_RA_WVLIM_STALL_HS = 0x000000a4, 3115 SPI_PERF_RA_WVLIM_STALL_LS = 0x000000a5, 3116 SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000a6, 3117 SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000a7, 3118 SPI_PERF_RA_PS_LOCK_NA = 0x000000a8, 3119 SPI_PERF_RA_VS_LOCK = 0x000000a9, 3120 SPI_PERF_RA_GS_LOCK = 0x000000aa, 3121 SPI_PERF_RA_ES_LOCK = 0x000000ab, 3122 SPI_PERF_RA_HS_LOCK = 0x000000ac, 3123 SPI_PERF_RA_LS_LOCK = 0x000000ad, 3124 SPI_PERF_RA_CSG_LOCK = 0x000000ae, 3125 SPI_PERF_RA_CSN_LOCK = 0x000000af, 3126 SPI_PERF_RA_RSV_UPD = 0x000000b0, 3127 SPI_PERF_EXP_ARB_COL_CNT = 0x000000b1, 3128 SPI_PERF_EXP_ARB_PAR_CNT = 0x000000b2, 3129 SPI_PERF_EXP_ARB_POS_CNT = 0x000000b3, 3130 SPI_PERF_EXP_ARB_GDS_CNT = 0x000000b4, 3131 SPI_PERF_CLKGATE_BUSY_STALL = 0x000000b5, 3132 SPI_PERF_CLKGATE_ACTIVE_STALL = 0x000000b6, 3133 SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0x000000b7, 3134 SPI_PERF_CLKGATE_CGTT_DYN_ON = 0x000000b8, 3135 SPI_PERF_CLKGATE_CGTT_REG_ON = 0x000000b9, 3136 SPI_PERF_NUM_VS_POS_EXPORTS = 0x000000ba, 3137 SPI_PERF_NUM_VS_PARAM_EXPORTS = 0x000000bb, 3138 SPI_PERF_NUM_PS_COL_EXPORTS = 0x000000bc, 3139 SPI_PERF_ES_GRP_FIFO_FULL = 0x000000bd, 3140 SPI_PERF_GS_GRP_FIFO_FULL = 0x000000be, 3141 SPI_PERF_HS_GRP_FIFO_FULL = 0x000000bf, 3142 SPI_PERF_LS_GRP_FIFO_FULL = 0x000000c0, 3143 SPI_PERF_VS_ALLOC_CNT = 0x000000c1, 3144 SPI_PERF_VS_LATE_ALLOC_ACCUM = 0x000000c2, 3145 SPI_PERF_PC_ALLOC_CNT = 0x000000c3, 3146 SPI_PERF_PC_ALLOC_ACCUM = 0x000000c4, 3147 } SPI_PERFCNT_SEL; 3148 3149 /* 3150 * SPI_SHADER_FORMAT enum 3151 */ 3152 3153 typedef enum SPI_SHADER_FORMAT { 3154 SPI_SHADER_NONE = 0x00000000, 3155 SPI_SHADER_1COMP = 0x00000001, 3156 SPI_SHADER_2COMP = 0x00000002, 3157 SPI_SHADER_4COMPRESS = 0x00000003, 3158 SPI_SHADER_4COMP = 0x00000004, 3159 } SPI_SHADER_FORMAT; 3160 3161 /* 3162 * SPI_SHADER_EX_FORMAT enum 3163 */ 3164 3165 typedef enum SPI_SHADER_EX_FORMAT { 3166 SPI_SHADER_ZERO = 0x00000000, 3167 SPI_SHADER_32_R = 0x00000001, 3168 SPI_SHADER_32_GR = 0x00000002, 3169 SPI_SHADER_32_AR = 0x00000003, 3170 SPI_SHADER_FP16_ABGR = 0x00000004, 3171 SPI_SHADER_UNORM16_ABGR = 0x00000005, 3172 SPI_SHADER_SNORM16_ABGR = 0x00000006, 3173 SPI_SHADER_UINT16_ABGR = 0x00000007, 3174 SPI_SHADER_SINT16_ABGR = 0x00000008, 3175 SPI_SHADER_32_ABGR = 0x00000009, 3176 } SPI_SHADER_EX_FORMAT; 3177 3178 /* 3179 * CLKGATE_SM_MODE enum 3180 */ 3181 3182 typedef enum CLKGATE_SM_MODE { 3183 ON_SEQ = 0x00000000, 3184 OFF_SEQ = 0x00000001, 3185 PROG_SEQ = 0x00000002, 3186 READ_SEQ = 0x00000003, 3187 SM_MODE_RESERVED = 0x00000004, 3188 } CLKGATE_SM_MODE; 3189 3190 /* 3191 * CLKGATE_BASE_MODE enum 3192 */ 3193 3194 typedef enum CLKGATE_BASE_MODE { 3195 MULT_8 = 0x00000000, 3196 MULT_16 = 0x00000001, 3197 } CLKGATE_BASE_MODE; 3198 3199 /******************************************************* 3200 * SQ Enums 3201 *******************************************************/ 3202 3203 /* 3204 * SQ_TEX_CLAMP enum 3205 */ 3206 3207 typedef enum SQ_TEX_CLAMP { 3208 SQ_TEX_WRAP = 0x00000000, 3209 SQ_TEX_MIRROR = 0x00000001, 3210 SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002, 3211 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003, 3212 SQ_TEX_CLAMP_HALF_BORDER = 0x00000004, 3213 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005, 3214 SQ_TEX_CLAMP_BORDER = 0x00000006, 3215 SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007, 3216 } SQ_TEX_CLAMP; 3217 3218 /* 3219 * SQ_TEX_XY_FILTER enum 3220 */ 3221 3222 typedef enum SQ_TEX_XY_FILTER { 3223 SQ_TEX_XY_FILTER_POINT = 0x00000000, 3224 SQ_TEX_XY_FILTER_BILINEAR = 0x00000001, 3225 SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002, 3226 SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003, 3227 } SQ_TEX_XY_FILTER; 3228 3229 /* 3230 * SQ_TEX_Z_FILTER enum 3231 */ 3232 3233 typedef enum SQ_TEX_Z_FILTER { 3234 SQ_TEX_Z_FILTER_NONE = 0x00000000, 3235 SQ_TEX_Z_FILTER_POINT = 0x00000001, 3236 SQ_TEX_Z_FILTER_LINEAR = 0x00000002, 3237 } SQ_TEX_Z_FILTER; 3238 3239 /* 3240 * SQ_TEX_MIP_FILTER enum 3241 */ 3242 3243 typedef enum SQ_TEX_MIP_FILTER { 3244 SQ_TEX_MIP_FILTER_NONE = 0x00000000, 3245 SQ_TEX_MIP_FILTER_POINT = 0x00000001, 3246 SQ_TEX_MIP_FILTER_LINEAR = 0x00000002, 3247 SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003, 3248 } SQ_TEX_MIP_FILTER; 3249 3250 /* 3251 * SQ_TEX_ANISO_RATIO enum 3252 */ 3253 3254 typedef enum SQ_TEX_ANISO_RATIO { 3255 SQ_TEX_ANISO_RATIO_1 = 0x00000000, 3256 SQ_TEX_ANISO_RATIO_2 = 0x00000001, 3257 SQ_TEX_ANISO_RATIO_4 = 0x00000002, 3258 SQ_TEX_ANISO_RATIO_8 = 0x00000003, 3259 SQ_TEX_ANISO_RATIO_16 = 0x00000004, 3260 } SQ_TEX_ANISO_RATIO; 3261 3262 /* 3263 * SQ_TEX_DEPTH_COMPARE enum 3264 */ 3265 3266 typedef enum SQ_TEX_DEPTH_COMPARE { 3267 SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000, 3268 SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001, 3269 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002, 3270 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003, 3271 SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004, 3272 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005, 3273 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006, 3274 SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007, 3275 } SQ_TEX_DEPTH_COMPARE; 3276 3277 /* 3278 * SQ_TEX_BORDER_COLOR enum 3279 */ 3280 3281 typedef enum SQ_TEX_BORDER_COLOR { 3282 SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000, 3283 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001, 3284 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002, 3285 SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003, 3286 } SQ_TEX_BORDER_COLOR; 3287 3288 /* 3289 * SQ_RSRC_BUF_TYPE enum 3290 */ 3291 3292 typedef enum SQ_RSRC_BUF_TYPE { 3293 SQ_RSRC_BUF = 0x00000000, 3294 SQ_RSRC_BUF_RSVD_1 = 0x00000001, 3295 SQ_RSRC_BUF_RSVD_2 = 0x00000002, 3296 SQ_RSRC_BUF_RSVD_3 = 0x00000003, 3297 } SQ_RSRC_BUF_TYPE; 3298 3299 /* 3300 * SQ_RSRC_IMG_TYPE enum 3301 */ 3302 3303 typedef enum SQ_RSRC_IMG_TYPE { 3304 SQ_RSRC_IMG_RSVD_0 = 0x00000000, 3305 SQ_RSRC_IMG_RSVD_1 = 0x00000001, 3306 SQ_RSRC_IMG_RSVD_2 = 0x00000002, 3307 SQ_RSRC_IMG_RSVD_3 = 0x00000003, 3308 SQ_RSRC_IMG_RSVD_4 = 0x00000004, 3309 SQ_RSRC_IMG_RSVD_5 = 0x00000005, 3310 SQ_RSRC_IMG_RSVD_6 = 0x00000006, 3311 SQ_RSRC_IMG_RSVD_7 = 0x00000007, 3312 SQ_RSRC_IMG_1D = 0x00000008, 3313 SQ_RSRC_IMG_2D = 0x00000009, 3314 SQ_RSRC_IMG_3D = 0x0000000a, 3315 SQ_RSRC_IMG_CUBE = 0x0000000b, 3316 SQ_RSRC_IMG_1D_ARRAY = 0x0000000c, 3317 SQ_RSRC_IMG_2D_ARRAY = 0x0000000d, 3318 SQ_RSRC_IMG_2D_MSAA = 0x0000000e, 3319 SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f, 3320 } SQ_RSRC_IMG_TYPE; 3321 3322 /* 3323 * SQ_RSRC_FLAT_TYPE enum 3324 */ 3325 3326 typedef enum SQ_RSRC_FLAT_TYPE { 3327 SQ_RSRC_FLAT_RSVD_0 = 0x00000000, 3328 SQ_RSRC_FLAT = 0x00000001, 3329 SQ_RSRC_FLAT_RSVD_2 = 0x00000002, 3330 SQ_RSRC_FLAT_RSVD_3 = 0x00000003, 3331 } SQ_RSRC_FLAT_TYPE; 3332 3333 /* 3334 * SQ_IMG_FILTER_TYPE enum 3335 */ 3336 3337 typedef enum SQ_IMG_FILTER_TYPE { 3338 SQ_IMG_FILTER_MODE_BLEND = 0x00000000, 3339 SQ_IMG_FILTER_MODE_MIN = 0x00000001, 3340 SQ_IMG_FILTER_MODE_MAX = 0x00000002, 3341 } SQ_IMG_FILTER_TYPE; 3342 3343 /* 3344 * SQ_SEL_XYZW01 enum 3345 */ 3346 3347 typedef enum SQ_SEL_XYZW01 { 3348 SQ_SEL_0 = 0x00000000, 3349 SQ_SEL_1 = 0x00000001, 3350 SQ_SEL_RESERVED_0 = 0x00000002, 3351 SQ_SEL_RESERVED_1 = 0x00000003, 3352 SQ_SEL_X = 0x00000004, 3353 SQ_SEL_Y = 0x00000005, 3354 SQ_SEL_Z = 0x00000006, 3355 SQ_SEL_W = 0x00000007, 3356 } SQ_SEL_XYZW01; 3357 3358 /* 3359 * SQ_WAVE_TYPE enum 3360 */ 3361 3362 typedef enum SQ_WAVE_TYPE { 3363 SQ_WAVE_TYPE_PS = 0x00000000, 3364 SQ_WAVE_TYPE_VS = 0x00000001, 3365 SQ_WAVE_TYPE_GS = 0x00000002, 3366 SQ_WAVE_TYPE_ES = 0x00000003, 3367 SQ_WAVE_TYPE_HS = 0x00000004, 3368 SQ_WAVE_TYPE_LS = 0x00000005, 3369 SQ_WAVE_TYPE_CS = 0x00000006, 3370 SQ_WAVE_TYPE_PS1 = 0x00000007, 3371 } SQ_WAVE_TYPE; 3372 3373 /* 3374 * SQ_THREAD_TRACE_TOKEN_TYPE enum 3375 */ 3376 3377 typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { 3378 SQ_THREAD_TRACE_TOKEN_MISC = 0x00000000, 3379 SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x00000001, 3380 SQ_THREAD_TRACE_TOKEN_REG = 0x00000002, 3381 SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x00000003, 3382 SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x00000004, 3383 SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x00000005, 3384 SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x00000006, 3385 SQ_THREAD_TRACE_TOKEN_EVENT = 0x00000007, 3386 SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x00000008, 3387 SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x00000009, 3388 SQ_THREAD_TRACE_TOKEN_INST = 0x0000000a, 3389 SQ_THREAD_TRACE_TOKEN_INST_PC = 0x0000000b, 3390 SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0x0000000c, 3391 SQ_THREAD_TRACE_TOKEN_ISSUE = 0x0000000d, 3392 SQ_THREAD_TRACE_TOKEN_PERF = 0x0000000e, 3393 SQ_THREAD_TRACE_TOKEN_REG_CS = 0x0000000f, 3394 } SQ_THREAD_TRACE_TOKEN_TYPE; 3395 3396 /* 3397 * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum 3398 */ 3399 3400 typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { 3401 SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x00000000, 3402 SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x00000001, 3403 SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x00000002, 3404 SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x00000003, 3405 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x00000004, 3406 SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x00000005, 3407 SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x00000006, 3408 SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x00000007, 3409 } SQ_THREAD_TRACE_MISC_TOKEN_TYPE; 3410 3411 /* 3412 * SQ_THREAD_TRACE_INST_TYPE enum 3413 */ 3414 3415 typedef enum SQ_THREAD_TRACE_INST_TYPE { 3416 SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x00000000, 3417 SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x00000001, 3418 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x00000002, 3419 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x00000003, 3420 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x00000004, 3421 SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x00000005, 3422 SQ_THREAD_TRACE_INST_TYPE_LDS = 0x00000006, 3423 SQ_THREAD_TRACE_INST_TYPE_PC = 0x00000007, 3424 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x00000008, 3425 SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x00000009, 3426 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a, 3427 SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b, 3428 SQ_THREAD_TRACE_INST_TYPE_JUMP = 0x0000000c, 3429 SQ_THREAD_TRACE_INST_TYPE_NEXT = 0x0000000d, 3430 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0x0000000e, 3431 SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0x0000000f, 3432 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x00000010, 3433 SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x00000011, 3434 SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x00000012, 3435 SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x00000013, 3436 SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x00000014, 3437 SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x00000015, 3438 SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x00000016, 3439 SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x00000017, 3440 SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x00000018, 3441 SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 0x00000019, 3442 } SQ_THREAD_TRACE_INST_TYPE; 3443 3444 /* 3445 * SQ_THREAD_TRACE_REG_TYPE enum 3446 */ 3447 3448 typedef enum SQ_THREAD_TRACE_REG_TYPE { 3449 SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x00000000, 3450 SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x00000001, 3451 SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x00000002, 3452 SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x00000003, 3453 SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x00000004, 3454 SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x00000005, 3455 SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x00000006, 3456 SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x00000007, 3457 } SQ_THREAD_TRACE_REG_TYPE; 3458 3459 /* 3460 * SQ_THREAD_TRACE_REG_OP enum 3461 */ 3462 3463 typedef enum SQ_THREAD_TRACE_REG_OP { 3464 SQ_THREAD_TRACE_REG_OP_READ = 0x00000000, 3465 SQ_THREAD_TRACE_REG_OP_WRITE = 0x00000001, 3466 } SQ_THREAD_TRACE_REG_OP; 3467 3468 /* 3469 * SQ_THREAD_TRACE_MODE_SEL enum 3470 */ 3471 3472 typedef enum SQ_THREAD_TRACE_MODE_SEL { 3473 SQ_THREAD_TRACE_MODE_OFF = 0x00000000, 3474 SQ_THREAD_TRACE_MODE_ON = 0x00000001, 3475 } SQ_THREAD_TRACE_MODE_SEL; 3476 3477 /* 3478 * SQ_THREAD_TRACE_CAPTURE_MODE enum 3479 */ 3480 3481 typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { 3482 SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x00000000, 3483 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x00000001, 3484 SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002, 3485 } SQ_THREAD_TRACE_CAPTURE_MODE; 3486 3487 /* 3488 * SQ_THREAD_TRACE_VM_ID_MASK enum 3489 */ 3490 3491 typedef enum SQ_THREAD_TRACE_VM_ID_MASK { 3492 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x00000000, 3493 SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x00000001, 3494 SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002, 3495 } SQ_THREAD_TRACE_VM_ID_MASK; 3496 3497 /* 3498 * SQ_THREAD_TRACE_WAVE_MASK enum 3499 */ 3500 3501 typedef enum SQ_THREAD_TRACE_WAVE_MASK { 3502 SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x00000000, 3503 SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x00000001, 3504 } SQ_THREAD_TRACE_WAVE_MASK; 3505 3506 /* 3507 * SQ_THREAD_TRACE_ISSUE enum 3508 */ 3509 3510 typedef enum SQ_THREAD_TRACE_ISSUE { 3511 SQ_THREAD_TRACE_ISSUE_NULL = 0x00000000, 3512 SQ_THREAD_TRACE_ISSUE_STALL = 0x00000001, 3513 SQ_THREAD_TRACE_ISSUE_INST = 0x00000002, 3514 SQ_THREAD_TRACE_ISSUE_IMMED = 0x00000003, 3515 } SQ_THREAD_TRACE_ISSUE; 3516 3517 /* 3518 * SQ_THREAD_TRACE_ISSUE_MASK enum 3519 */ 3520 3521 typedef enum SQ_THREAD_TRACE_ISSUE_MASK { 3522 SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x00000000, 3523 SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x00000001, 3524 SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002, 3525 SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x00000003, 3526 } SQ_THREAD_TRACE_ISSUE_MASK; 3527 3528 /* 3529 * SQ_PERF_SEL enum 3530 */ 3531 3532 typedef enum SQ_PERF_SEL { 3533 SQ_PERF_SEL_NONE = 0x00000000, 3534 SQ_PERF_SEL_ACCUM_PREV = 0x00000001, 3535 SQ_PERF_SEL_CYCLES = 0x00000002, 3536 SQ_PERF_SEL_BUSY_CYCLES = 0x00000003, 3537 SQ_PERF_SEL_WAVES = 0x00000004, 3538 SQ_PERF_SEL_LEVEL_WAVES = 0x00000005, 3539 SQ_PERF_SEL_WAVES_EQ_64 = 0x00000006, 3540 SQ_PERF_SEL_WAVES_LT_64 = 0x00000007, 3541 SQ_PERF_SEL_WAVES_LT_48 = 0x00000008, 3542 SQ_PERF_SEL_WAVES_LT_32 = 0x00000009, 3543 SQ_PERF_SEL_WAVES_LT_16 = 0x0000000a, 3544 SQ_PERF_SEL_WAVES_CU = 0x0000000b, 3545 SQ_PERF_SEL_LEVEL_WAVES_CU = 0x0000000c, 3546 SQ_PERF_SEL_BUSY_CU_CYCLES = 0x0000000d, 3547 SQ_PERF_SEL_ITEMS = 0x0000000e, 3548 SQ_PERF_SEL_QUADS = 0x0000000f, 3549 SQ_PERF_SEL_EVENTS = 0x00000010, 3550 SQ_PERF_SEL_SURF_SYNCS = 0x00000011, 3551 SQ_PERF_SEL_TTRACE_REQS = 0x00000012, 3552 SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x00000013, 3553 SQ_PERF_SEL_TTRACE_STALL = 0x00000014, 3554 SQ_PERF_SEL_MSG_CNTR = 0x00000015, 3555 SQ_PERF_SEL_MSG_PERF = 0x00000016, 3556 SQ_PERF_SEL_MSG_GSCNT = 0x00000017, 3557 SQ_PERF_SEL_MSG_INTERRUPT = 0x00000018, 3558 SQ_PERF_SEL_INSTS = 0x00000019, 3559 SQ_PERF_SEL_INSTS_VALU = 0x0000001a, 3560 SQ_PERF_SEL_INSTS_VMEM_WR = 0x0000001b, 3561 SQ_PERF_SEL_INSTS_VMEM_RD = 0x0000001c, 3562 SQ_PERF_SEL_INSTS_VMEM = 0x0000001d, 3563 SQ_PERF_SEL_INSTS_SALU = 0x0000001e, 3564 SQ_PERF_SEL_INSTS_SMEM = 0x0000001f, 3565 SQ_PERF_SEL_INSTS_FLAT = 0x00000020, 3566 SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x00000021, 3567 SQ_PERF_SEL_INSTS_LDS = 0x00000022, 3568 SQ_PERF_SEL_INSTS_GDS = 0x00000023, 3569 SQ_PERF_SEL_INSTS_EXP = 0x00000024, 3570 SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000025, 3571 SQ_PERF_SEL_INSTS_BRANCH = 0x00000026, 3572 SQ_PERF_SEL_INSTS_SENDMSG = 0x00000027, 3573 SQ_PERF_SEL_INSTS_VSKIPPED = 0x00000028, 3574 SQ_PERF_SEL_INST_LEVEL_VMEM = 0x00000029, 3575 SQ_PERF_SEL_INST_LEVEL_SMEM = 0x0000002a, 3576 SQ_PERF_SEL_INST_LEVEL_LDS = 0x0000002b, 3577 SQ_PERF_SEL_INST_LEVEL_GDS = 0x0000002c, 3578 SQ_PERF_SEL_INST_LEVEL_EXP = 0x0000002d, 3579 SQ_PERF_SEL_WAVE_CYCLES = 0x0000002e, 3580 SQ_PERF_SEL_WAVE_READY = 0x0000002f, 3581 SQ_PERF_SEL_WAIT_CNT_VM = 0x00000030, 3582 SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000031, 3583 SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000032, 3584 SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000033, 3585 SQ_PERF_SEL_WAIT_BARRIER = 0x00000034, 3586 SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x00000035, 3587 SQ_PERF_SEL_WAIT_SLEEP = 0x00000036, 3588 SQ_PERF_SEL_WAIT_SLEEP_XNACK = 0x00000037, 3589 SQ_PERF_SEL_WAIT_OTHER = 0x00000038, 3590 SQ_PERF_SEL_WAIT_ANY = 0x00000039, 3591 SQ_PERF_SEL_WAIT_TTRACE = 0x0000003a, 3592 SQ_PERF_SEL_WAIT_IFETCH = 0x0000003b, 3593 SQ_PERF_SEL_WAIT_INST_ANY = 0x0000003c, 3594 SQ_PERF_SEL_WAIT_INST_VMEM = 0x0000003d, 3595 SQ_PERF_SEL_WAIT_INST_SCA = 0x0000003e, 3596 SQ_PERF_SEL_WAIT_INST_LDS = 0x0000003f, 3597 SQ_PERF_SEL_WAIT_INST_VALU = 0x00000040, 3598 SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000041, 3599 SQ_PERF_SEL_WAIT_INST_MISC = 0x00000042, 3600 SQ_PERF_SEL_WAIT_INST_FLAT = 0x00000043, 3601 SQ_PERF_SEL_ACTIVE_INST_ANY = 0x00000044, 3602 SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x00000045, 3603 SQ_PERF_SEL_ACTIVE_INST_LDS = 0x00000046, 3604 SQ_PERF_SEL_ACTIVE_INST_VALU = 0x00000047, 3605 SQ_PERF_SEL_ACTIVE_INST_SCA = 0x00000048, 3606 SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x00000049, 3607 SQ_PERF_SEL_ACTIVE_INST_MISC = 0x0000004a, 3608 SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x0000004b, 3609 SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x0000004c, 3610 SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x0000004d, 3611 SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x0000004e, 3612 SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x0000004f, 3613 SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x00000050, 3614 SQ_PERF_SEL_INST_CYCLES_EXP = 0x00000051, 3615 SQ_PERF_SEL_INST_CYCLES_GDS = 0x00000052, 3616 SQ_PERF_SEL_INST_CYCLES_SMEM = 0x00000053, 3617 SQ_PERF_SEL_INST_CYCLES_SALU = 0x00000054, 3618 SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x00000055, 3619 SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x00000056, 3620 SQ_PERF_SEL_IFETCH = 0x00000057, 3621 SQ_PERF_SEL_IFETCH_LEVEL = 0x00000058, 3622 SQ_PERF_SEL_CBRANCH_FORK = 0x00000059, 3623 SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x0000005a, 3624 SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x0000005b, 3625 SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x0000005c, 3626 SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x0000005d, 3627 SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x0000005e, 3628 SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x0000005f, 3629 SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000060, 3630 SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000061, 3631 SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x00000062, 3632 SQ_PERF_SEL_VALU_DEP_STALL = 0x00000063, 3633 SQ_PERF_SEL_VALU_STARVE = 0x00000064, 3634 SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000065, 3635 SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x00000066, 3636 SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x00000067, 3637 SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x00000068, 3638 SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x00000069, 3639 SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x0000006a, 3640 SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x0000006b, 3641 SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x0000006c, 3642 SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x0000006d, 3643 SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x0000006e, 3644 SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x0000006f, 3645 SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x00000070, 3646 SQ_PERF_SEL_SRC_CD_BUSY = 0x00000071, 3647 SQ_PERF_SEL_PT_POWER_STALL = 0x00000072, 3648 SQ_PERF_SEL_USER0 = 0x00000073, 3649 SQ_PERF_SEL_USER1 = 0x00000074, 3650 SQ_PERF_SEL_USER2 = 0x00000075, 3651 SQ_PERF_SEL_USER3 = 0x00000076, 3652 SQ_PERF_SEL_USER4 = 0x00000077, 3653 SQ_PERF_SEL_USER5 = 0x00000078, 3654 SQ_PERF_SEL_USER6 = 0x00000079, 3655 SQ_PERF_SEL_USER7 = 0x0000007a, 3656 SQ_PERF_SEL_USER8 = 0x0000007b, 3657 SQ_PERF_SEL_USER9 = 0x0000007c, 3658 SQ_PERF_SEL_USER10 = 0x0000007d, 3659 SQ_PERF_SEL_USER11 = 0x0000007e, 3660 SQ_PERF_SEL_USER12 = 0x0000007f, 3661 SQ_PERF_SEL_USER13 = 0x00000080, 3662 SQ_PERF_SEL_USER14 = 0x00000081, 3663 SQ_PERF_SEL_USER15 = 0x00000082, 3664 SQ_PERF_SEL_USER_LEVEL0 = 0x00000083, 3665 SQ_PERF_SEL_USER_LEVEL1 = 0x00000084, 3666 SQ_PERF_SEL_USER_LEVEL2 = 0x00000085, 3667 SQ_PERF_SEL_USER_LEVEL3 = 0x00000086, 3668 SQ_PERF_SEL_USER_LEVEL4 = 0x00000087, 3669 SQ_PERF_SEL_USER_LEVEL5 = 0x00000088, 3670 SQ_PERF_SEL_USER_LEVEL6 = 0x00000089, 3671 SQ_PERF_SEL_USER_LEVEL7 = 0x0000008a, 3672 SQ_PERF_SEL_USER_LEVEL8 = 0x0000008b, 3673 SQ_PERF_SEL_USER_LEVEL9 = 0x0000008c, 3674 SQ_PERF_SEL_USER_LEVEL10 = 0x0000008d, 3675 SQ_PERF_SEL_USER_LEVEL11 = 0x0000008e, 3676 SQ_PERF_SEL_USER_LEVEL12 = 0x0000008f, 3677 SQ_PERF_SEL_USER_LEVEL13 = 0x00000090, 3678 SQ_PERF_SEL_USER_LEVEL14 = 0x00000091, 3679 SQ_PERF_SEL_USER_LEVEL15 = 0x00000092, 3680 SQ_PERF_SEL_POWER_VALU = 0x00000093, 3681 SQ_PERF_SEL_POWER_VALU0 = 0x00000094, 3682 SQ_PERF_SEL_POWER_VALU1 = 0x00000095, 3683 SQ_PERF_SEL_POWER_VALU2 = 0x00000096, 3684 SQ_PERF_SEL_POWER_GPR_RD = 0x00000097, 3685 SQ_PERF_SEL_POWER_GPR_WR = 0x00000098, 3686 SQ_PERF_SEL_POWER_LDS_BUSY = 0x00000099, 3687 SQ_PERF_SEL_POWER_ALU_BUSY = 0x0000009a, 3688 SQ_PERF_SEL_POWER_TEX_BUSY = 0x0000009b, 3689 SQ_PERF_SEL_ACCUM_PREV_HIRES = 0x0000009c, 3690 SQ_PERF_SEL_WAVES_RESTORED = 0x0000009d, 3691 SQ_PERF_SEL_WAVES_SAVED = 0x0000009e, 3692 SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000009f, 3693 SQ_PERF_SEL_ATC_INSTS_VMEM = 0x000000a0, 3694 SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x000000a1, 3695 SQ_PERF_SEL_ATC_XNACK_FIRST = 0x000000a2, 3696 SQ_PERF_SEL_ATC_XNACK_ALL = 0x000000a3, 3697 SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x000000a4, 3698 SQ_PERF_SEL_ATC_INSTS_SMEM = 0x000000a5, 3699 SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x000000a6, 3700 SQ_PERF_SEL_IFETCH_XNACK = 0x000000a7, 3701 SQ_PERF_SEL_TLB_SHOOTDOWN = 0x000000a8, 3702 SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x000000a9, 3703 SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x000000aa, 3704 SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x000000ab, 3705 SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x000000ac, 3706 SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x000000ad, 3707 SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x000000ae, 3708 SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x000000af, 3709 SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x000000b0, 3710 SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x000000b1, 3711 SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000b2, 3712 SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000b3, 3713 SQ_PERF_SEL_UTCL1_REQUEST = 0x000000b4, 3714 SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b5, 3715 SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b6, 3716 SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b7, 3717 SQ_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b8, 3718 SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b9, 3719 SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000ba, 3720 SQ_PERF_SEL_DUMMY_END = 0x000000bb, 3721 SQ_PERF_SEL_DUMMY_LAST = 0x000000ff, 3722 SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0x00000100, 3723 SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000101, 3724 SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0x00000102, 3725 SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0x00000103, 3726 SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000104, 3727 SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0x00000105, 3728 SQC_PERF_SEL_TC_REQ = 0x00000106, 3729 SQC_PERF_SEL_TC_INST_REQ = 0x00000107, 3730 SQC_PERF_SEL_TC_DATA_READ_REQ = 0x00000108, 3731 SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0x00000109, 3732 SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0x0000010a, 3733 SQC_PERF_SEL_TC_STALL = 0x0000010b, 3734 SQC_PERF_SEL_TC_STARVE = 0x0000010c, 3735 SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000010d, 3736 SQC_PERF_SEL_ICACHE_REQ = 0x0000010e, 3737 SQC_PERF_SEL_ICACHE_HITS = 0x0000010f, 3738 SQC_PERF_SEL_ICACHE_MISSES = 0x00000110, 3739 SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000111, 3740 SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000112, 3741 SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000113, 3742 SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000114, 3743 SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000115, 3744 SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000116, 3745 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x00000117, 3746 SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000118, 3747 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0x00000119, 3748 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000011a, 3749 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x0000011b, 3750 SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000011c, 3751 SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000011d, 3752 SQC_PERF_SEL_ICACHE_PREFETCH_1 = 0x0000011e, 3753 SQC_PERF_SEL_ICACHE_PREFETCH_2 = 0x0000011f, 3754 SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 0x00000120, 3755 SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000121, 3756 SQC_PERF_SEL_DCACHE_REQ = 0x00000122, 3757 SQC_PERF_SEL_DCACHE_HITS = 0x00000123, 3758 SQC_PERF_SEL_DCACHE_MISSES = 0x00000124, 3759 SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000125, 3760 SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x00000126, 3761 SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0x00000127, 3762 SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0x00000128, 3763 SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0x00000129, 3764 SQC_PERF_SEL_DCACHE_ATOMIC = 0x0000012a, 3765 SQC_PERF_SEL_DCACHE_VOLATILE = 0x0000012b, 3766 SQC_PERF_SEL_DCACHE_INVAL_INST = 0x0000012c, 3767 SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000012d, 3768 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0x0000012e, 3769 SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0x0000012f, 3770 SQC_PERF_SEL_DCACHE_WB_INST = 0x00000130, 3771 SQC_PERF_SEL_DCACHE_WB_ASYNC = 0x00000131, 3772 SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0x00000132, 3773 SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0x00000133, 3774 SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000134, 3775 SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x00000135, 3776 SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x00000136, 3777 SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000137, 3778 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000138, 3779 SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0x00000139, 3780 SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0x0000013a, 3781 SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 0x0000013b, 3782 SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0x0000013c, 3783 SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0x0000013d, 3784 SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0x0000013e, 3785 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000013f, 3786 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x00000140, 3787 SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0x00000141, 3788 SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000142, 3789 SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000143, 3790 SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000144, 3791 SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000145, 3792 SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000146, 3793 SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000147, 3794 SQC_PERF_SEL_DCACHE_REQ_TIME = 0x00000148, 3795 SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0x00000149, 3796 SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0x0000014a, 3797 SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0x0000014b, 3798 SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x0000014c, 3799 SQC_PERF_SEL_SQ_DCACHE_REQS = 0x0000014d, 3800 SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x0000014e, 3801 SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0x0000014f, 3802 SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000150, 3803 SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000151, 3804 SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000152, 3805 SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000153, 3806 SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000154, 3807 SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0x00000155, 3808 SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0x00000156, 3809 SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0x00000157, 3810 SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000158, 3811 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000159, 3812 SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0x0000015a, 3813 SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x0000015b, 3814 SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x0000015c, 3815 SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x0000015d, 3816 SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x0000015e, 3817 SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x0000015f, 3818 SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x00000160, 3819 SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x00000161, 3820 SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x00000162, 3821 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x00000163, 3822 SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x00000164, 3823 SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x00000165, 3824 SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 0x00000166, 3825 SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x00000167, 3826 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x00000168, 3827 SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x00000169, 3828 SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x0000016a, 3829 SQC_PERF_SEL_DUMMY_LAST = 0x0000016b, 3830 } SQ_PERF_SEL; 3831 3832 /* 3833 * SQ_CAC_POWER_SEL enum 3834 */ 3835 3836 typedef enum SQ_CAC_POWER_SEL { 3837 SQ_CAC_POWER_VALU = 0x00000000, 3838 SQ_CAC_POWER_VALU0 = 0x00000001, 3839 SQ_CAC_POWER_VALU1 = 0x00000002, 3840 SQ_CAC_POWER_VALU2 = 0x00000003, 3841 SQ_CAC_POWER_GPR_RD = 0x00000004, 3842 SQ_CAC_POWER_GPR_WR = 0x00000005, 3843 SQ_CAC_POWER_LDS_BUSY = 0x00000006, 3844 SQ_CAC_POWER_ALU_BUSY = 0x00000007, 3845 SQ_CAC_POWER_TEX_BUSY = 0x00000008, 3846 } SQ_CAC_POWER_SEL; 3847 3848 /* 3849 * SQ_IND_CMD_CMD enum 3850 */ 3851 3852 typedef enum SQ_IND_CMD_CMD { 3853 SQ_IND_CMD_CMD_NULL = 0x00000000, 3854 SQ_IND_CMD_CMD_SETHALT = 0x00000001, 3855 SQ_IND_CMD_CMD_SAVECTX = 0x00000002, 3856 SQ_IND_CMD_CMD_KILL = 0x00000003, 3857 SQ_IND_CMD_CMD_DEBUG = 0x00000004, 3858 SQ_IND_CMD_CMD_TRAP = 0x00000005, 3859 SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006, 3860 SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007, 3861 } SQ_IND_CMD_CMD; 3862 3863 /* 3864 * SQ_IND_CMD_MODE enum 3865 */ 3866 3867 typedef enum SQ_IND_CMD_MODE { 3868 SQ_IND_CMD_MODE_SINGLE = 0x00000000, 3869 SQ_IND_CMD_MODE_BROADCAST = 0x00000001, 3870 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, 3871 SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, 3872 SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, 3873 } SQ_IND_CMD_MODE; 3874 3875 /* 3876 * SQ_EDC_INFO_SOURCE enum 3877 */ 3878 3879 typedef enum SQ_EDC_INFO_SOURCE { 3880 SQ_EDC_INFO_SOURCE_INVALID = 0x00000000, 3881 SQ_EDC_INFO_SOURCE_INST = 0x00000001, 3882 SQ_EDC_INFO_SOURCE_SGPR = 0x00000002, 3883 SQ_EDC_INFO_SOURCE_VGPR = 0x00000003, 3884 SQ_EDC_INFO_SOURCE_LDS = 0x00000004, 3885 SQ_EDC_INFO_SOURCE_GDS = 0x00000005, 3886 SQ_EDC_INFO_SOURCE_TA = 0x00000006, 3887 } SQ_EDC_INFO_SOURCE; 3888 3889 /* 3890 * SQ_ROUND_MODE enum 3891 */ 3892 3893 typedef enum SQ_ROUND_MODE { 3894 SQ_ROUND_NEAREST_EVEN = 0x00000000, 3895 SQ_ROUND_PLUS_INFINITY = 0x00000001, 3896 SQ_ROUND_MINUS_INFINITY = 0x00000002, 3897 SQ_ROUND_TO_ZERO = 0x00000003, 3898 } SQ_ROUND_MODE; 3899 3900 /* 3901 * SQ_INTERRUPT_WORD_ENCODING enum 3902 */ 3903 3904 typedef enum SQ_INTERRUPT_WORD_ENCODING { 3905 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000, 3906 SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001, 3907 SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002, 3908 } SQ_INTERRUPT_WORD_ENCODING; 3909 3910 /* 3911 * ENUM_SQ_EXPORT_RAT_INST enum 3912 */ 3913 3914 typedef enum ENUM_SQ_EXPORT_RAT_INST { 3915 SQ_EXPORT_RAT_INST_NOP = 0x00000000, 3916 SQ_EXPORT_RAT_INST_STORE_TYPED = 0x00000001, 3917 SQ_EXPORT_RAT_INST_STORE_RAW = 0x00000002, 3918 SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x00000003, 3919 SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x00000004, 3920 SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x00000005, 3921 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x00000006, 3922 SQ_EXPORT_RAT_INST_ADD = 0x00000007, 3923 SQ_EXPORT_RAT_INST_SUB = 0x00000008, 3924 SQ_EXPORT_RAT_INST_RSUB = 0x00000009, 3925 SQ_EXPORT_RAT_INST_MIN_INT = 0x0000000a, 3926 SQ_EXPORT_RAT_INST_MIN_UINT = 0x0000000b, 3927 SQ_EXPORT_RAT_INST_MAX_INT = 0x0000000c, 3928 SQ_EXPORT_RAT_INST_MAX_UINT = 0x0000000d, 3929 SQ_EXPORT_RAT_INST_AND = 0x0000000e, 3930 SQ_EXPORT_RAT_INST_OR = 0x0000000f, 3931 SQ_EXPORT_RAT_INST_XOR = 0x00000010, 3932 SQ_EXPORT_RAT_INST_MSKOR = 0x00000011, 3933 SQ_EXPORT_RAT_INST_INC_UINT = 0x00000012, 3934 SQ_EXPORT_RAT_INST_DEC_UINT = 0x00000013, 3935 SQ_EXPORT_RAT_INST_STORE_DWORD = 0x00000014, 3936 SQ_EXPORT_RAT_INST_STORE_SHORT = 0x00000015, 3937 SQ_EXPORT_RAT_INST_STORE_BYTE = 0x00000016, 3938 SQ_EXPORT_RAT_INST_NOP_RTN = 0x00000020, 3939 SQ_EXPORT_RAT_INST_XCHG_RTN = 0x00000022, 3940 SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x00000023, 3941 SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x00000024, 3942 SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x00000025, 3943 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x00000026, 3944 SQ_EXPORT_RAT_INST_ADD_RTN = 0x00000027, 3945 SQ_EXPORT_RAT_INST_SUB_RTN = 0x00000028, 3946 SQ_EXPORT_RAT_INST_RSUB_RTN = 0x00000029, 3947 SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x0000002a, 3948 SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x0000002b, 3949 SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x0000002c, 3950 SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x0000002d, 3951 SQ_EXPORT_RAT_INST_AND_RTN = 0x0000002e, 3952 SQ_EXPORT_RAT_INST_OR_RTN = 0x0000002f, 3953 SQ_EXPORT_RAT_INST_XOR_RTN = 0x00000030, 3954 SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x00000031, 3955 SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x00000032, 3956 SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x00000033, 3957 } ENUM_SQ_EXPORT_RAT_INST; 3958 3959 /* 3960 * SQ_IBUF_ST enum 3961 */ 3962 3963 typedef enum SQ_IBUF_ST { 3964 SQ_IBUF_IB_IDLE = 0x00000000, 3965 SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001, 3966 SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002, 3967 SQ_IBUF_IB_LE_4DW = 0x00000003, 3968 SQ_IBUF_IB_WAIT_DRET = 0x00000004, 3969 SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005, 3970 SQ_IBUF_IB_DRET = 0x00000006, 3971 SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007, 3972 } SQ_IBUF_ST; 3973 3974 /* 3975 * SQ_INST_STR_ST enum 3976 */ 3977 3978 typedef enum SQ_INST_STR_ST { 3979 SQ_INST_STR_IB_WAVE_NORML = 0x00000000, 3980 SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001, 3981 SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002, 3982 SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003, 3983 SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004, 3984 SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005, 3985 SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006, 3986 SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007, 3987 } SQ_INST_STR_ST; 3988 3989 /* 3990 * SQ_WAVE_IB_ECC_ST enum 3991 */ 3992 3993 typedef enum SQ_WAVE_IB_ECC_ST { 3994 SQ_WAVE_IB_ECC_CLEAN = 0x00000000, 3995 SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001, 3996 SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002, 3997 SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003, 3998 } SQ_WAVE_IB_ECC_ST; 3999 4000 /* 4001 * SH_MEM_ADDRESS_MODE enum 4002 */ 4003 4004 typedef enum SH_MEM_ADDRESS_MODE { 4005 SH_MEM_ADDRESS_MODE_64 = 0x00000000, 4006 SH_MEM_ADDRESS_MODE_32 = 0x00000001, 4007 } SH_MEM_ADDRESS_MODE; 4008 4009 /* 4010 * SH_MEM_ALIGNMENT_MODE enum 4011 */ 4012 4013 typedef enum SH_MEM_ALIGNMENT_MODE { 4014 SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, 4015 SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001, 4016 SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002, 4017 SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003, 4018 } SH_MEM_ALIGNMENT_MODE; 4019 4020 /* 4021 * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum 4022 */ 4023 4024 typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX { 4025 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018, 4026 SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019, 4027 } SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX; 4028 4029 /* 4030 * SQ_LB_CTR_SEL_VALUES enum 4031 */ 4032 4033 typedef enum SQ_LB_CTR_SEL_VALUES { 4034 SQ_LB_CTR_SEL_ALU_CYCLES = 0x00000000, 4035 SQ_LB_CTR_SEL_ALU_STALLS = 0x00000001, 4036 SQ_LB_CTR_SEL_TEX_CYCLES = 0x00000002, 4037 SQ_LB_CTR_SEL_TEX_STALLS = 0x00000003, 4038 SQ_LB_CTR_SEL_SALU_CYCLES = 0x00000004, 4039 SQ_LB_CTR_SEL_SCALAR_STALLS = 0x00000005, 4040 SQ_LB_CTR_SEL_SMEM_CYCLES = 0x00000006, 4041 SQ_LB_CTR_SEL_ICACHE_STALLS = 0x00000007, 4042 SQ_LB_CTR_SEL_DCACHE_STALLS = 0x00000008, 4043 SQ_LB_CTR_SEL_RESERVED0 = 0x00000009, 4044 SQ_LB_CTR_SEL_RESERVED1 = 0x0000000a, 4045 SQ_LB_CTR_SEL_RESERVED2 = 0x0000000b, 4046 SQ_LB_CTR_SEL_RESERVED3 = 0x0000000c, 4047 SQ_LB_CTR_SEL_RESERVED4 = 0x0000000d, 4048 SQ_LB_CTR_SEL_RESERVED5 = 0x0000000e, 4049 SQ_LB_CTR_SEL_RESERVED6 = 0x0000000f, 4050 } SQ_LB_CTR_SEL_VALUES; 4051 4052 /* 4053 * SQ_WAVE_TYPE value 4054 */ 4055 4056 #define SQ_WAVE_TYPE_PS0 0x00000000 4057 4058 /* 4059 * SQIND_PARTITIONS value 4060 */ 4061 4062 #define SQIND_GLOBAL_REGS_OFFSET 0x00000000 4063 #define SQIND_GLOBAL_REGS_SIZE 0x00000008 4064 #define SQIND_LOCAL_REGS_OFFSET 0x00000008 4065 #define SQIND_LOCAL_REGS_SIZE 0x00000008 4066 #define SQIND_WAVE_HWREGS_OFFSET 0x00000010 4067 #define SQIND_WAVE_HWREGS_SIZE 0x000001f0 4068 #define SQIND_WAVE_SGPRS_OFFSET 0x00000200 4069 #define SQIND_WAVE_SGPRS_SIZE 0x00000200 4070 #define SQIND_WAVE_VGPRS_OFFSET 0x00000400 4071 #define SQIND_WAVE_VGPRS_SIZE 0x00000100 4072 4073 /* 4074 * SQ_GFXDEC value 4075 */ 4076 4077 #define SQ_GFXDEC_BEGIN 0x0000a000 4078 #define SQ_GFXDEC_END 0x0000c000 4079 #define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a 4080 4081 /* 4082 * SQDEC value 4083 */ 4084 4085 #define SQDEC_BEGIN 0x00002300 4086 #define SQDEC_END 0x000023ff 4087 4088 /* 4089 * SQPERFSDEC value 4090 */ 4091 4092 #define SQPERFSDEC_BEGIN 0x0000d9c0 4093 #define SQPERFSDEC_END 0x0000da40 4094 4095 /* 4096 * SQPERFDDEC value 4097 */ 4098 4099 #define SQPERFDDEC_BEGIN 0x0000d1c0 4100 #define SQPERFDDEC_END 0x0000d240 4101 4102 /* 4103 * SQGFXUDEC value 4104 */ 4105 4106 #define SQGFXUDEC_BEGIN 0x0000c330 4107 #define SQGFXUDEC_END 0x0000c380 4108 4109 /* 4110 * SQPWRDEC value 4111 */ 4112 4113 #define SQPWRDEC_BEGIN 0x0000f08c 4114 #define SQPWRDEC_END 0x0000f094 4115 4116 /* 4117 * SQ_DISPATCHER value 4118 */ 4119 4120 #define SQ_DISPATCHER_GFX_MIN 0x00000010 4121 #define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008 4122 4123 /* 4124 * SQ_MAX value 4125 */ 4126 4127 #define SQ_MAX_PGM_SGPRS 0x00000068 4128 #define SQ_MAX_PGM_VGPRS 0x00000100 4129 4130 /* 4131 * SQ_THREAD_TRACE_TIME_UNIT value 4132 */ 4133 4134 #define SQ_THREAD_TRACE_TIME_UNIT 0x00000004 4135 4136 /* 4137 * SQ_EXCP_BITS value 4138 */ 4139 4140 #define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000 4141 #define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007 4142 #define SQ_EX_MODE_EXCP_INVALID 0x00000000 4143 #define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001 4144 #define SQ_EX_MODE_EXCP_DIV0 0x00000002 4145 #define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003 4146 #define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004 4147 #define SQ_EX_MODE_EXCP_INEXACT 0x00000005 4148 #define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006 4149 #define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007 4150 #define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008 4151 4152 /* 4153 * SQ_EXCP_HI_BITS value 4154 */ 4155 4156 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000 4157 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001 4158 #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002 4159 4160 /* 4161 * HW_INSERTED_INST_ID value 4162 */ 4163 4164 #define INST_ID_PRIV_START 0x80000000 4165 #define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 4166 #define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 4167 #define INST_ID_HW_TRAP 0xfffffff2 4168 #define INST_ID_KILL_SEQ 0xfffffff3 4169 #define INST_ID_SPI_WREXEC 0xfffffff4 4170 #define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe 4171 4172 /* 4173 * SIMM16_WAITCNT_PARTITIONS value 4174 */ 4175 4176 #define SIMM16_WAITCNT_VM_CNT_START 0x00000000 4177 #define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000004 4178 #define SIMM16_WAITCNT_EXP_CNT_START 0x00000004 4179 #define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003 4180 #define SIMM16_WAITCNT_LGKM_CNT_START 0x00000008 4181 #define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000004 4182 #define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e 4183 #define SIMM16_WAITCNT_VM_CNT_HI_SIZE 0x00000002 4184 4185 /* 4186 * SQ_EDC_FUE_CNTL_BITS value 4187 */ 4188 4189 #define SQ_EDC_FUE_CNTL_SQ 0x00000000 4190 #define SQ_EDC_FUE_CNTL_LDS 0x00000001 4191 #define SQ_EDC_FUE_CNTL_SIMD0 0x00000002 4192 #define SQ_EDC_FUE_CNTL_SIMD1 0x00000003 4193 #define SQ_EDC_FUE_CNTL_SIMD2 0x00000004 4194 #define SQ_EDC_FUE_CNTL_SIMD3 0x00000005 4195 #define SQ_EDC_FUE_CNTL_TA 0x00000006 4196 #define SQ_EDC_FUE_CNTL_TD 0x00000007 4197 #define SQ_EDC_FUE_CNTL_TCP 0x00000008 4198 4199 /******************************************************* 4200 * COMP Enums 4201 *******************************************************/ 4202 4203 /* 4204 * CSDATA_TYPE enum 4205 */ 4206 4207 typedef enum CSDATA_TYPE { 4208 CSDATA_TYPE_TG = 0x00000000, 4209 CSDATA_TYPE_STATE = 0x00000001, 4210 CSDATA_TYPE_EVENT = 0x00000002, 4211 CSDATA_TYPE_PRIVATE = 0x00000003, 4212 } CSDATA_TYPE; 4213 4214 /* 4215 * CSDATA_TYPE_WIDTH value 4216 */ 4217 4218 #define CSDATA_TYPE_WIDTH 0x00000002 4219 4220 /* 4221 * CSDATA_ADDR_WIDTH value 4222 */ 4223 4224 #define CSDATA_ADDR_WIDTH 0x00000007 4225 4226 /* 4227 * CSDATA_DATA_WIDTH value 4228 */ 4229 4230 #define CSDATA_DATA_WIDTH 0x00000020 4231 4232 /******************************************************* 4233 * VGT Enums 4234 *******************************************************/ 4235 4236 /* 4237 * VGT_OUT_PRIM_TYPE enum 4238 */ 4239 4240 typedef enum VGT_OUT_PRIM_TYPE { 4241 VGT_OUT_POINT = 0x00000000, 4242 VGT_OUT_LINE = 0x00000001, 4243 VGT_OUT_TRI = 0x00000002, 4244 VGT_OUT_RECT_V0 = 0x00000003, 4245 VGT_OUT_RECT_V1 = 0x00000004, 4246 VGT_OUT_RECT_V2 = 0x00000005, 4247 VGT_OUT_RECT_V3 = 0x00000006, 4248 VGT_OUT_2D_RECT = 0x00000007, 4249 VGT_TE_QUAD = 0x00000008, 4250 VGT_TE_PRIM_INDEX_LINE = 0x00000009, 4251 VGT_TE_PRIM_INDEX_TRI = 0x0000000a, 4252 VGT_TE_PRIM_INDEX_QUAD = 0x0000000b, 4253 VGT_OUT_LINE_ADJ = 0x0000000c, 4254 VGT_OUT_TRI_ADJ = 0x0000000d, 4255 VGT_OUT_PATCH = 0x0000000e, 4256 } VGT_OUT_PRIM_TYPE; 4257 4258 /* 4259 * VGT_DI_PRIM_TYPE enum 4260 */ 4261 4262 typedef enum VGT_DI_PRIM_TYPE { 4263 DI_PT_NONE = 0x00000000, 4264 DI_PT_POINTLIST = 0x00000001, 4265 DI_PT_LINELIST = 0x00000002, 4266 DI_PT_LINESTRIP = 0x00000003, 4267 DI_PT_TRILIST = 0x00000004, 4268 DI_PT_TRIFAN = 0x00000005, 4269 DI_PT_TRISTRIP = 0x00000006, 4270 DI_PT_2D_RECTANGLE = 0x00000007, 4271 DI_PT_UNUSED_1 = 0x00000008, 4272 DI_PT_PATCH = 0x00000009, 4273 DI_PT_LINELIST_ADJ = 0x0000000a, 4274 DI_PT_LINESTRIP_ADJ = 0x0000000b, 4275 DI_PT_TRILIST_ADJ = 0x0000000c, 4276 DI_PT_TRISTRIP_ADJ = 0x0000000d, 4277 DI_PT_UNUSED_3 = 0x0000000e, 4278 DI_PT_UNUSED_4 = 0x0000000f, 4279 DI_PT_TRI_WITH_WFLAGS = 0x00000010, 4280 DI_PT_RECTLIST = 0x00000011, 4281 DI_PT_LINELOOP = 0x00000012, 4282 DI_PT_QUADLIST = 0x00000013, 4283 DI_PT_QUADSTRIP = 0x00000014, 4284 DI_PT_POLYGON = 0x00000015, 4285 } VGT_DI_PRIM_TYPE; 4286 4287 /* 4288 * VGT_DI_SOURCE_SELECT enum 4289 */ 4290 4291 typedef enum VGT_DI_SOURCE_SELECT { 4292 DI_SRC_SEL_DMA = 0x00000000, 4293 DI_SRC_SEL_IMMEDIATE = 0x00000001, 4294 DI_SRC_SEL_AUTO_INDEX = 0x00000002, 4295 DI_SRC_SEL_RESERVED = 0x00000003, 4296 } VGT_DI_SOURCE_SELECT; 4297 4298 /* 4299 * VGT_DI_MAJOR_MODE_SELECT enum 4300 */ 4301 4302 typedef enum VGT_DI_MAJOR_MODE_SELECT { 4303 DI_MAJOR_MODE_0 = 0x00000000, 4304 DI_MAJOR_MODE_1 = 0x00000001, 4305 } VGT_DI_MAJOR_MODE_SELECT; 4306 4307 /* 4308 * VGT_DI_INDEX_SIZE enum 4309 */ 4310 4311 typedef enum VGT_DI_INDEX_SIZE { 4312 DI_INDEX_SIZE_16_BIT = 0x00000000, 4313 DI_INDEX_SIZE_32_BIT = 0x00000001, 4314 DI_INDEX_SIZE_8_BIT = 0x00000002, 4315 } VGT_DI_INDEX_SIZE; 4316 4317 /* 4318 * VGT_EVENT_TYPE enum 4319 */ 4320 4321 typedef enum VGT_EVENT_TYPE { 4322 Reserved_0x00 = 0x00000000, 4323 SAMPLE_STREAMOUTSTATS1 = 0x00000001, 4324 SAMPLE_STREAMOUTSTATS2 = 0x00000002, 4325 SAMPLE_STREAMOUTSTATS3 = 0x00000003, 4326 CACHE_FLUSH_TS = 0x00000004, 4327 CONTEXT_DONE = 0x00000005, 4328 CACHE_FLUSH = 0x00000006, 4329 CS_PARTIAL_FLUSH = 0x00000007, 4330 VGT_STREAMOUT_SYNC = 0x00000008, 4331 Reserved_0x09 = 0x00000009, 4332 VGT_STREAMOUT_RESET = 0x0000000a, 4333 END_OF_PIPE_INCR_DE = 0x0000000b, 4334 END_OF_PIPE_IB_END = 0x0000000c, 4335 RST_PIX_CNT = 0x0000000d, 4336 BREAK_BATCH = 0x0000000e, 4337 VS_PARTIAL_FLUSH = 0x0000000f, 4338 PS_PARTIAL_FLUSH = 0x00000010, 4339 FLUSH_HS_OUTPUT = 0x00000011, 4340 FLUSH_DFSM = 0x00000012, 4341 RESET_TO_LOWEST_VGT = 0x00000013, 4342 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014, 4343 ZPASS_DONE = 0x00000015, 4344 CACHE_FLUSH_AND_INV_EVENT = 0x00000016, 4345 PERFCOUNTER_START = 0x00000017, 4346 PERFCOUNTER_STOP = 0x00000018, 4347 PIPELINESTAT_START = 0x00000019, 4348 PIPELINESTAT_STOP = 0x0000001a, 4349 PERFCOUNTER_SAMPLE = 0x0000001b, 4350 Available_0x1c = 0x0000001c, 4351 Available_0x1d = 0x0000001d, 4352 SAMPLE_PIPELINESTAT = 0x0000001e, 4353 SO_VGTSTREAMOUT_FLUSH = 0x0000001f, 4354 SAMPLE_STREAMOUTSTATS = 0x00000020, 4355 RESET_VTX_CNT = 0x00000021, 4356 BLOCK_CONTEXT_DONE = 0x00000022, 4357 CS_CONTEXT_DONE = 0x00000023, 4358 VGT_FLUSH = 0x00000024, 4359 TGID_ROLLOVER = 0x00000025, 4360 SQ_NON_EVENT = 0x00000026, 4361 SC_SEND_DB_VPZ = 0x00000027, 4362 BOTTOM_OF_PIPE_TS = 0x00000028, 4363 FLUSH_SX_TS = 0x00000029, 4364 DB_CACHE_FLUSH_AND_INV = 0x0000002a, 4365 FLUSH_AND_INV_DB_DATA_TS = 0x0000002b, 4366 FLUSH_AND_INV_DB_META = 0x0000002c, 4367 FLUSH_AND_INV_CB_DATA_TS = 0x0000002d, 4368 FLUSH_AND_INV_CB_META = 0x0000002e, 4369 CS_DONE = 0x0000002f, 4370 PS_DONE = 0x00000030, 4371 FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031, 4372 SX_CB_RAT_ACK_REQUEST = 0x00000032, 4373 THREAD_TRACE_START = 0x00000033, 4374 THREAD_TRACE_STOP = 0x00000034, 4375 THREAD_TRACE_MARKER = 0x00000035, 4376 THREAD_TRACE_FLUSH = 0x00000036, 4377 THREAD_TRACE_FINISH = 0x00000037, 4378 PIXEL_PIPE_STAT_CONTROL = 0x00000038, 4379 PIXEL_PIPE_STAT_DUMP = 0x00000039, 4380 PIXEL_PIPE_STAT_RESET = 0x0000003a, 4381 CONTEXT_SUSPEND = 0x0000003b, 4382 OFFCHIP_HS_DEALLOC = 0x0000003c, 4383 ENABLE_NGG_PIPELINE = 0x0000003d, 4384 ENABLE_LEGACY_PIPELINE = 0x0000003e, 4385 Reserved_0x3f = 0x0000003f, 4386 } VGT_EVENT_TYPE; 4387 4388 /* 4389 * VGT_DMA_SWAP_MODE enum 4390 */ 4391 4392 typedef enum VGT_DMA_SWAP_MODE { 4393 VGT_DMA_SWAP_NONE = 0x00000000, 4394 VGT_DMA_SWAP_16_BIT = 0x00000001, 4395 VGT_DMA_SWAP_32_BIT = 0x00000002, 4396 VGT_DMA_SWAP_WORD = 0x00000003, 4397 } VGT_DMA_SWAP_MODE; 4398 4399 /* 4400 * VGT_INDEX_TYPE_MODE enum 4401 */ 4402 4403 typedef enum VGT_INDEX_TYPE_MODE { 4404 VGT_INDEX_16 = 0x00000000, 4405 VGT_INDEX_32 = 0x00000001, 4406 VGT_INDEX_8 = 0x00000002, 4407 } VGT_INDEX_TYPE_MODE; 4408 4409 /* 4410 * VGT_DMA_BUF_TYPE enum 4411 */ 4412 4413 typedef enum VGT_DMA_BUF_TYPE { 4414 VGT_DMA_BUF_MEM = 0x00000000, 4415 VGT_DMA_BUF_RING = 0x00000001, 4416 VGT_DMA_BUF_SETUP = 0x00000002, 4417 VGT_DMA_PTR_UPDATE = 0x00000003, 4418 } VGT_DMA_BUF_TYPE; 4419 4420 /* 4421 * VGT_OUTPATH_SELECT enum 4422 */ 4423 4424 typedef enum VGT_OUTPATH_SELECT { 4425 VGT_OUTPATH_VTX_REUSE = 0x00000000, 4426 VGT_OUTPATH_TESS_EN = 0x00000001, 4427 VGT_OUTPATH_PASSTHRU = 0x00000002, 4428 VGT_OUTPATH_GS_BLOCK = 0x00000003, 4429 VGT_OUTPATH_HS_BLOCK = 0x00000004, 4430 VGT_OUTPATH_PRIM_GEN = 0x00000005, 4431 } VGT_OUTPATH_SELECT; 4432 4433 /* 4434 * VGT_GRP_PRIM_TYPE enum 4435 */ 4436 4437 typedef enum VGT_GRP_PRIM_TYPE { 4438 VGT_GRP_3D_POINT = 0x00000000, 4439 VGT_GRP_3D_LINE = 0x00000001, 4440 VGT_GRP_3D_TRI = 0x00000002, 4441 VGT_GRP_3D_RECT = 0x00000003, 4442 VGT_GRP_3D_QUAD = 0x00000004, 4443 VGT_GRP_2D_COPY_RECT_V0 = 0x00000005, 4444 VGT_GRP_2D_COPY_RECT_V1 = 0x00000006, 4445 VGT_GRP_2D_COPY_RECT_V2 = 0x00000007, 4446 VGT_GRP_2D_COPY_RECT_V3 = 0x00000008, 4447 VGT_GRP_2D_FILL_RECT = 0x00000009, 4448 VGT_GRP_2D_LINE = 0x0000000a, 4449 VGT_GRP_2D_TRI = 0x0000000b, 4450 VGT_GRP_PRIM_INDEX_LINE = 0x0000000c, 4451 VGT_GRP_PRIM_INDEX_TRI = 0x0000000d, 4452 VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e, 4453 VGT_GRP_3D_LINE_ADJ = 0x0000000f, 4454 VGT_GRP_3D_TRI_ADJ = 0x00000010, 4455 VGT_GRP_3D_PATCH = 0x00000011, 4456 VGT_GRP_2D_RECT = 0x00000012, 4457 } VGT_GRP_PRIM_TYPE; 4458 4459 /* 4460 * VGT_GRP_PRIM_ORDER enum 4461 */ 4462 4463 typedef enum VGT_GRP_PRIM_ORDER { 4464 VGT_GRP_LIST = 0x00000000, 4465 VGT_GRP_STRIP = 0x00000001, 4466 VGT_GRP_FAN = 0x00000002, 4467 VGT_GRP_LOOP = 0x00000003, 4468 VGT_GRP_POLYGON = 0x00000004, 4469 } VGT_GRP_PRIM_ORDER; 4470 4471 /* 4472 * VGT_GROUP_CONV_SEL enum 4473 */ 4474 4475 typedef enum VGT_GROUP_CONV_SEL { 4476 VGT_GRP_INDEX_16 = 0x00000000, 4477 VGT_GRP_INDEX_32 = 0x00000001, 4478 VGT_GRP_UINT_16 = 0x00000002, 4479 VGT_GRP_UINT_32 = 0x00000003, 4480 VGT_GRP_SINT_16 = 0x00000004, 4481 VGT_GRP_SINT_32 = 0x00000005, 4482 VGT_GRP_FLOAT_32 = 0x00000006, 4483 VGT_GRP_AUTO_PRIM = 0x00000007, 4484 VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008, 4485 } VGT_GROUP_CONV_SEL; 4486 4487 /* 4488 * VGT_GS_MODE_TYPE enum 4489 */ 4490 4491 typedef enum VGT_GS_MODE_TYPE { 4492 GS_OFF = 0x00000000, 4493 GS_SCENARIO_A = 0x00000001, 4494 GS_SCENARIO_B = 0x00000002, 4495 GS_SCENARIO_G = 0x00000003, 4496 GS_SCENARIO_C = 0x00000004, 4497 SPRITE_EN = 0x00000005, 4498 } VGT_GS_MODE_TYPE; 4499 4500 /* 4501 * VGT_GS_CUT_MODE enum 4502 */ 4503 4504 typedef enum VGT_GS_CUT_MODE { 4505 GS_CUT_1024 = 0x00000000, 4506 GS_CUT_512 = 0x00000001, 4507 GS_CUT_256 = 0x00000002, 4508 GS_CUT_128 = 0x00000003, 4509 } VGT_GS_CUT_MODE; 4510 4511 /* 4512 * VGT_GS_OUTPRIM_TYPE enum 4513 */ 4514 4515 typedef enum VGT_GS_OUTPRIM_TYPE { 4516 POINTLIST = 0x00000000, 4517 LINESTRIP = 0x00000001, 4518 TRISTRIP = 0x00000002, 4519 RECTLIST = 0x00000003, 4520 } VGT_GS_OUTPRIM_TYPE; 4521 4522 /* 4523 * VGT_CACHE_INVALID_MODE enum 4524 */ 4525 4526 typedef enum VGT_CACHE_INVALID_MODE { 4527 VC_ONLY = 0x00000000, 4528 TC_ONLY = 0x00000001, 4529 VC_AND_TC = 0x00000002, 4530 } VGT_CACHE_INVALID_MODE; 4531 4532 /* 4533 * VGT_TESS_TYPE enum 4534 */ 4535 4536 typedef enum VGT_TESS_TYPE { 4537 TESS_ISOLINE = 0x00000000, 4538 TESS_TRIANGLE = 0x00000001, 4539 TESS_QUAD = 0x00000002, 4540 } VGT_TESS_TYPE; 4541 4542 /* 4543 * VGT_TESS_PARTITION enum 4544 */ 4545 4546 typedef enum VGT_TESS_PARTITION { 4547 PART_INTEGER = 0x00000000, 4548 PART_POW2 = 0x00000001, 4549 PART_FRAC_ODD = 0x00000002, 4550 PART_FRAC_EVEN = 0x00000003, 4551 } VGT_TESS_PARTITION; 4552 4553 /* 4554 * VGT_TESS_TOPOLOGY enum 4555 */ 4556 4557 typedef enum VGT_TESS_TOPOLOGY { 4558 OUTPUT_POINT = 0x00000000, 4559 OUTPUT_LINE = 0x00000001, 4560 OUTPUT_TRIANGLE_CW = 0x00000002, 4561 OUTPUT_TRIANGLE_CCW = 0x00000003, 4562 } VGT_TESS_TOPOLOGY; 4563 4564 /* 4565 * VGT_RDREQ_POLICY enum 4566 */ 4567 4568 typedef enum VGT_RDREQ_POLICY { 4569 VGT_POLICY_LRU = 0x00000000, 4570 VGT_POLICY_STREAM = 0x00000001, 4571 } VGT_RDREQ_POLICY; 4572 4573 /* 4574 * VGT_DIST_MODE enum 4575 */ 4576 4577 typedef enum VGT_DIST_MODE { 4578 NO_DIST = 0x00000000, 4579 PATCHES = 0x00000001, 4580 DONUTS = 0x00000002, 4581 TRAPEZOIDS = 0x00000003, 4582 } VGT_DIST_MODE; 4583 4584 /* 4585 * VGT_STAGES_LS_EN enum 4586 */ 4587 4588 typedef enum VGT_STAGES_LS_EN { 4589 LS_STAGE_OFF = 0x00000000, 4590 LS_STAGE_ON = 0x00000001, 4591 CS_STAGE_ON = 0x00000002, 4592 RESERVED_LS = 0x00000003, 4593 } VGT_STAGES_LS_EN; 4594 4595 /* 4596 * VGT_STAGES_HS_EN enum 4597 */ 4598 4599 typedef enum VGT_STAGES_HS_EN { 4600 HS_STAGE_OFF = 0x00000000, 4601 HS_STAGE_ON = 0x00000001, 4602 } VGT_STAGES_HS_EN; 4603 4604 /* 4605 * VGT_STAGES_ES_EN enum 4606 */ 4607 4608 typedef enum VGT_STAGES_ES_EN { 4609 ES_STAGE_OFF = 0x00000000, 4610 ES_STAGE_DS = 0x00000001, 4611 ES_STAGE_REAL = 0x00000002, 4612 RESERVED_ES = 0x00000003, 4613 } VGT_STAGES_ES_EN; 4614 4615 /* 4616 * VGT_STAGES_GS_EN enum 4617 */ 4618 4619 typedef enum VGT_STAGES_GS_EN { 4620 GS_STAGE_OFF = 0x00000000, 4621 GS_STAGE_ON = 0x00000001, 4622 } VGT_STAGES_GS_EN; 4623 4624 /* 4625 * VGT_STAGES_VS_EN enum 4626 */ 4627 4628 typedef enum VGT_STAGES_VS_EN { 4629 VS_STAGE_REAL = 0x00000000, 4630 VS_STAGE_DS = 0x00000001, 4631 VS_STAGE_COPY_SHADER = 0x00000002, 4632 RESERVED_VS = 0x00000003, 4633 } VGT_STAGES_VS_EN; 4634 4635 /* 4636 * VGT_PERFCOUNT_SELECT enum 4637 */ 4638 4639 typedef enum VGT_PERFCOUNT_SELECT { 4640 vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x00000000, 4641 vgt_perf_VGT_SPI_ESVERT_VALID = 0x00000001, 4642 vgt_perf_VGT_SPI_ESVERT_EOV = 0x00000002, 4643 vgt_perf_VGT_SPI_ESVERT_STALLED = 0x00000003, 4644 vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x00000004, 4645 vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x00000005, 4646 vgt_perf_VGT_SPI_ESVERT_STATIC = 0x00000006, 4647 vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x00000007, 4648 vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x00000008, 4649 vgt_perf_VGT_SPI_GSPRIM_VALID = 0x00000009, 4650 vgt_perf_VGT_SPI_GSPRIM_EOV = 0x0000000a, 4651 vgt_perf_VGT_SPI_GSPRIM_CONT = 0x0000000b, 4652 vgt_perf_VGT_SPI_GSPRIM_STALLED = 0x0000000c, 4653 vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0x0000000d, 4654 vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0x0000000e, 4655 vgt_perf_VGT_SPI_GSPRIM_STATIC = 0x0000000f, 4656 vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000010, 4657 vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x00000011, 4658 vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x00000012, 4659 vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x00000013, 4660 vgt_perf_VGT_SPI_VSVERT_SEND = 0x00000014, 4661 vgt_perf_VGT_SPI_VSVERT_EOV = 0x00000015, 4662 vgt_perf_VGT_SPI_VSVERT_STALLED = 0x00000016, 4663 vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x00000017, 4664 vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x00000018, 4665 vgt_perf_VGT_SPI_VSVERT_STATIC = 0x00000019, 4666 vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x0000001a, 4667 vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x0000001b, 4668 vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x0000001c, 4669 vgt_perf_VGT_PA_CLIPV_SEND = 0x0000001d, 4670 vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x0000001e, 4671 vgt_perf_VGT_PA_CLIPV_STALLED = 0x0000001f, 4672 vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x00000020, 4673 vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x00000021, 4674 vgt_perf_VGT_PA_CLIPV_STATIC = 0x00000022, 4675 vgt_perf_VGT_PA_CLIPP_SEND = 0x00000023, 4676 vgt_perf_VGT_PA_CLIPP_EOP = 0x00000024, 4677 vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x00000025, 4678 vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x00000026, 4679 vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x00000027, 4680 vgt_perf_VGT_PA_CLIPP_STALLED = 0x00000028, 4681 vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x00000029, 4682 vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x0000002a, 4683 vgt_perf_VGT_PA_CLIPP_STATIC = 0x0000002b, 4684 vgt_perf_VGT_PA_CLIPS_SEND = 0x0000002c, 4685 vgt_perf_VGT_PA_CLIPS_STALLED = 0x0000002d, 4686 vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x0000002e, 4687 vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x0000002f, 4688 vgt_perf_VGT_PA_CLIPS_STATIC = 0x00000030, 4689 vgt_perf_vsvert_ds_send = 0x00000031, 4690 vgt_perf_vsvert_api_send = 0x00000032, 4691 vgt_perf_hs_tif_stall = 0x00000033, 4692 vgt_perf_hs_input_stall = 0x00000034, 4693 vgt_perf_hs_interface_stall = 0x00000035, 4694 vgt_perf_hs_tfm_stall = 0x00000036, 4695 vgt_perf_te11_starved = 0x00000037, 4696 vgt_perf_gs_event_stall = 0x00000038, 4697 vgt_perf_vgt_pa_clipp_send_not_event = 0x00000039, 4698 vgt_perf_vgt_pa_clipp_valid_prim = 0x0000003a, 4699 vgt_perf_reused_es_indices = 0x0000003b, 4700 vgt_perf_vs_cache_hits = 0x0000003c, 4701 vgt_perf_gs_cache_hits = 0x0000003d, 4702 vgt_perf_ds_cache_hits = 0x0000003e, 4703 vgt_perf_total_cache_hits = 0x0000003f, 4704 vgt_perf_vgt_busy = 0x00000040, 4705 vgt_perf_vgt_gs_busy = 0x00000041, 4706 vgt_perf_esvert_stalled_es_tbl = 0x00000042, 4707 vgt_perf_esvert_stalled_gs_tbl = 0x00000043, 4708 vgt_perf_esvert_stalled_gs_event = 0x00000044, 4709 vgt_perf_esvert_stalled_gsprim = 0x00000045, 4710 vgt_perf_gsprim_stalled_es_tbl = 0x00000046, 4711 vgt_perf_gsprim_stalled_gs_tbl = 0x00000047, 4712 vgt_perf_gsprim_stalled_gs_event = 0x00000048, 4713 vgt_perf_gsprim_stalled_esvert = 0x00000049, 4714 vgt_perf_esthread_stalled_es_rb_full = 0x0000004a, 4715 vgt_perf_esthread_stalled_spi_bp = 0x0000004b, 4716 vgt_perf_counters_avail_stalled = 0x0000004c, 4717 vgt_perf_gs_rb_space_avail_stalled = 0x0000004d, 4718 vgt_perf_gs_issue_rtr_stalled = 0x0000004e, 4719 vgt_perf_gsthread_stalled = 0x0000004f, 4720 vgt_perf_strmout_stalled = 0x00000050, 4721 vgt_perf_wait_for_es_done_stalled = 0x00000051, 4722 vgt_perf_cm_stalled_by_gog = 0x00000052, 4723 vgt_perf_cm_reading_stalled = 0x00000053, 4724 vgt_perf_cm_stalled_by_gsfetch_done = 0x00000054, 4725 vgt_perf_gog_vs_tbl_stalled = 0x00000055, 4726 vgt_perf_gog_out_indx_stalled = 0x00000056, 4727 vgt_perf_gog_out_prim_stalled = 0x00000057, 4728 vgt_perf_waveid_stalled = 0x00000058, 4729 vgt_perf_gog_busy = 0x00000059, 4730 vgt_perf_reused_vs_indices = 0x0000005a, 4731 vgt_perf_sclk_reg_vld_event = 0x0000005b, 4732 vgt_perf_vs_conflicting_indices = 0x0000005c, 4733 vgt_perf_sclk_core_vld_event = 0x0000005d, 4734 vgt_perf_hswave_stalled = 0x0000005e, 4735 vgt_perf_sclk_gs_vld_event = 0x0000005f, 4736 vgt_perf_VGT_SPI_LSVERT_VALID = 0x00000060, 4737 vgt_perf_VGT_SPI_LSVERT_EOV = 0x00000061, 4738 vgt_perf_VGT_SPI_LSVERT_STALLED = 0x00000062, 4739 vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x00000063, 4740 vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x00000064, 4741 vgt_perf_VGT_SPI_LSVERT_STATIC = 0x00000065, 4742 vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x00000066, 4743 vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x00000067, 4744 vgt_perf_VGT_SPI_LSWAVE_SEND = 0x00000068, 4745 vgt_perf_VGT_SPI_HSVERT_VALID = 0x00000069, 4746 vgt_perf_VGT_SPI_HSVERT_EOV = 0x0000006a, 4747 vgt_perf_VGT_SPI_HSVERT_STALLED = 0x0000006b, 4748 vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x0000006c, 4749 vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x0000006d, 4750 vgt_perf_VGT_SPI_HSVERT_STATIC = 0x0000006e, 4751 vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x0000006f, 4752 vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x00000070, 4753 vgt_perf_VGT_SPI_HSWAVE_SEND = 0x00000071, 4754 vgt_perf_ds_prims = 0x00000072, 4755 vgt_perf_ds_RESERVED = 0x00000073, 4756 vgt_perf_ls_thread_groups = 0x00000074, 4757 vgt_perf_hs_thread_groups = 0x00000075, 4758 vgt_perf_es_thread_groups = 0x00000076, 4759 vgt_perf_vs_thread_groups = 0x00000077, 4760 vgt_perf_ls_done_latency = 0x00000078, 4761 vgt_perf_hs_done_latency = 0x00000079, 4762 vgt_perf_es_done_latency = 0x0000007a, 4763 vgt_perf_gs_done_latency = 0x0000007b, 4764 vgt_perf_vgt_hs_busy = 0x0000007c, 4765 vgt_perf_vgt_te11_busy = 0x0000007d, 4766 vgt_perf_ls_flush = 0x0000007e, 4767 vgt_perf_hs_flush = 0x0000007f, 4768 vgt_perf_es_flush = 0x00000080, 4769 vgt_perf_vgt_pa_clipp_eopg = 0x00000081, 4770 vgt_perf_ls_done = 0x00000082, 4771 vgt_perf_hs_done = 0x00000083, 4772 vgt_perf_es_done = 0x00000084, 4773 vgt_perf_gs_done = 0x00000085, 4774 vgt_perf_vsfetch_done = 0x00000086, 4775 vgt_perf_gs_done_received = 0x00000087, 4776 vgt_perf_es_ring_high_water_mark = 0x00000088, 4777 vgt_perf_gs_ring_high_water_mark = 0x00000089, 4778 vgt_perf_vs_table_high_water_mark = 0x0000008a, 4779 vgt_perf_hs_tgs_active_high_water_mark = 0x0000008b, 4780 vgt_perf_pa_clipp_dealloc = 0x0000008c, 4781 vgt_perf_cut_mem_flush_stalled = 0x0000008d, 4782 vgt_perf_vsvert_work_received = 0x0000008e, 4783 vgt_perf_vgt_pa_clipp_starved_after_work = 0x0000008f, 4784 vgt_perf_te11_con_starved_after_work = 0x00000090, 4785 vgt_perf_hs_waiting_on_ls_done_stall = 0x00000091, 4786 vgt_spi_vsvert_valid = 0x00000092, 4787 } VGT_PERFCOUNT_SELECT; 4788 4789 /* 4790 * IA_PERFCOUNT_SELECT enum 4791 */ 4792 4793 typedef enum IA_PERFCOUNT_SELECT { 4794 ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x00000000, 4795 ia_perf_dma_data_fifo_full = 0x00000001, 4796 ia_perf_RESERVED1 = 0x00000002, 4797 ia_perf_RESERVED2 = 0x00000003, 4798 ia_perf_RESERVED3 = 0x00000004, 4799 ia_perf_RESERVED4 = 0x00000005, 4800 ia_perf_RESERVED5 = 0x00000006, 4801 ia_perf_MC_LAT_BIN_0 = 0x00000007, 4802 ia_perf_MC_LAT_BIN_1 = 0x00000008, 4803 ia_perf_MC_LAT_BIN_2 = 0x00000009, 4804 ia_perf_MC_LAT_BIN_3 = 0x0000000a, 4805 ia_perf_MC_LAT_BIN_4 = 0x0000000b, 4806 ia_perf_MC_LAT_BIN_5 = 0x0000000c, 4807 ia_perf_MC_LAT_BIN_6 = 0x0000000d, 4808 ia_perf_MC_LAT_BIN_7 = 0x0000000e, 4809 ia_perf_ia_busy = 0x0000000f, 4810 ia_perf_ia_sclk_reg_vld_event = 0x00000010, 4811 ia_perf_RESERVED6 = 0x00000011, 4812 ia_perf_ia_sclk_core_vld_event = 0x00000012, 4813 ia_perf_RESERVED7 = 0x00000013, 4814 ia_perf_ia_dma_return = 0x00000014, 4815 ia_perf_ia_stalled = 0x00000015, 4816 ia_perf_shift_starved_pipe0_event = 0x00000016, 4817 ia_perf_shift_starved_pipe1_event = 0x00000017, 4818 } IA_PERFCOUNT_SELECT; 4819 4820 /* 4821 * WD_PERFCOUNT_SELECT enum 4822 */ 4823 4824 typedef enum WD_PERFCOUNT_SELECT { 4825 wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x00000000, 4826 wd_perf_RBIU_DR_FIFO_STARVED = 0x00000001, 4827 wd_perf_RBIU_DR_FIFO_STALLED = 0x00000002, 4828 wd_perf_RBIU_DI_FIFO_STARVED = 0x00000003, 4829 wd_perf_RBIU_DI_FIFO_STALLED = 0x00000004, 4830 wd_perf_wd_busy = 0x00000005, 4831 wd_perf_wd_sclk_reg_vld_event = 0x00000006, 4832 wd_perf_wd_sclk_input_vld_event = 0x00000007, 4833 wd_perf_wd_sclk_core_vld_event = 0x00000008, 4834 wd_perf_wd_stalled = 0x00000009, 4835 wd_perf_inside_tf_bin_0 = 0x0000000a, 4836 wd_perf_inside_tf_bin_1 = 0x0000000b, 4837 wd_perf_inside_tf_bin_2 = 0x0000000c, 4838 wd_perf_inside_tf_bin_3 = 0x0000000d, 4839 wd_perf_inside_tf_bin_4 = 0x0000000e, 4840 wd_perf_inside_tf_bin_5 = 0x0000000f, 4841 wd_perf_inside_tf_bin_6 = 0x00000010, 4842 wd_perf_inside_tf_bin_7 = 0x00000011, 4843 wd_perf_inside_tf_bin_8 = 0x00000012, 4844 wd_perf_tfreq_lat_bin_0 = 0x00000013, 4845 wd_perf_tfreq_lat_bin_1 = 0x00000014, 4846 wd_perf_tfreq_lat_bin_2 = 0x00000015, 4847 wd_perf_tfreq_lat_bin_3 = 0x00000016, 4848 wd_perf_tfreq_lat_bin_4 = 0x00000017, 4849 wd_perf_tfreq_lat_bin_5 = 0x00000018, 4850 wd_perf_tfreq_lat_bin_6 = 0x00000019, 4851 wd_perf_tfreq_lat_bin_7 = 0x0000001a, 4852 wd_starved_on_hs_done = 0x0000001b, 4853 wd_perf_se0_hs_done_latency = 0x0000001c, 4854 wd_perf_se1_hs_done_latency = 0x0000001d, 4855 wd_perf_se2_hs_done_latency = 0x0000001e, 4856 wd_perf_se3_hs_done_latency = 0x0000001f, 4857 wd_perf_hs_done_se0 = 0x00000020, 4858 wd_perf_hs_done_se1 = 0x00000021, 4859 wd_perf_hs_done_se2 = 0x00000022, 4860 wd_perf_hs_done_se3 = 0x00000023, 4861 wd_perf_null_patches = 0x00000024, 4862 } WD_PERFCOUNT_SELECT; 4863 4864 /* 4865 * WD_IA_DRAW_TYPE enum 4866 */ 4867 4868 typedef enum WD_IA_DRAW_TYPE { 4869 WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000, 4870 WD_IA_DRAW_TYPE_REG_XFER = 0x00000001, 4871 WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002, 4872 WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003, 4873 WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004, 4874 WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005, 4875 WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006, 4876 WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007, 4877 } WD_IA_DRAW_TYPE; 4878 4879 /* 4880 * WD_IA_DRAW_REG_XFER enum 4881 */ 4882 4883 typedef enum WD_IA_DRAW_REG_XFER { 4884 WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000, 4885 WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001, 4886 } WD_IA_DRAW_REG_XFER; 4887 4888 /* 4889 * WD_IA_DRAW_SOURCE enum 4890 */ 4891 4892 typedef enum WD_IA_DRAW_SOURCE { 4893 WD_IA_DRAW_SOURCE_DMA = 0x00000000, 4894 WD_IA_DRAW_SOURCE_IMMD = 0x00000001, 4895 WD_IA_DRAW_SOURCE_AUTO = 0x00000002, 4896 WD_IA_DRAW_SOURCE_OPAQ = 0x00000003, 4897 } WD_IA_DRAW_SOURCE; 4898 4899 /* 4900 * GS_THREADID_SIZE value 4901 */ 4902 4903 #define GSTHREADID_SIZE 0x00000002 4904 4905 /******************************************************* 4906 * GB Enums 4907 *******************************************************/ 4908 4909 /* 4910 * GB_EDC_DED_MODE enum 4911 */ 4912 4913 typedef enum GB_EDC_DED_MODE { 4914 GB_EDC_DED_MODE_LOG = 0x00000000, 4915 GB_EDC_DED_MODE_HALT = 0x00000001, 4916 GB_EDC_DED_MODE_INT_HALT = 0x00000002, 4917 } GB_EDC_DED_MODE; 4918 4919 /* 4920 * VALUE_GB_TILING_CONFIG_TABLE_SIZE value 4921 */ 4922 4923 #define GB_TILING_CONFIG_TABLE_SIZE 0x00000020 4924 4925 /* 4926 * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value 4927 */ 4928 4929 #define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010 4930 4931 /******************************************************* 4932 * TP Enums 4933 *******************************************************/ 4934 4935 /* 4936 * TA_TC_ADDR_MODES enum 4937 */ 4938 4939 typedef enum TA_TC_ADDR_MODES { 4940 TA_TC_ADDR_MODE_DEFAULT = 0x00000000, 4941 TA_TC_ADDR_MODE_COMP0 = 0x00000001, 4942 TA_TC_ADDR_MODE_COMP1 = 0x00000002, 4943 TA_TC_ADDR_MODE_COMP2 = 0x00000003, 4944 TA_TC_ADDR_MODE_COMP3 = 0x00000004, 4945 TA_TC_ADDR_MODE_UNALIGNED = 0x00000005, 4946 TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006, 4947 } TA_TC_ADDR_MODES; 4948 4949 /* 4950 * TA_PERFCOUNT_SEL enum 4951 */ 4952 4953 typedef enum TA_PERFCOUNT_SEL { 4954 TA_PERF_SEL_NULL = 0x00000000, 4955 TA_PERF_SEL_sh_fifo_busy = 0x00000001, 4956 TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002, 4957 TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003, 4958 TA_PERF_SEL_sh_fifo_data_busy = 0x00000004, 4959 TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005, 4960 TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006, 4961 TA_PERF_SEL_gradient_busy = 0x00000007, 4962 TA_PERF_SEL_gradient_fifo_busy = 0x00000008, 4963 TA_PERF_SEL_lod_busy = 0x00000009, 4964 TA_PERF_SEL_lod_fifo_busy = 0x0000000a, 4965 TA_PERF_SEL_addresser_busy = 0x0000000b, 4966 TA_PERF_SEL_addresser_fifo_busy = 0x0000000c, 4967 TA_PERF_SEL_aligner_busy = 0x0000000d, 4968 TA_PERF_SEL_write_path_busy = 0x0000000e, 4969 TA_PERF_SEL_ta_busy = 0x0000000f, 4970 TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010, 4971 TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011, 4972 TA_PERF_SEL_sp_ta_data_cycles = 0x00000012, 4973 TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013, 4974 TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014, 4975 TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015, 4976 TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 0x00000016, 4977 TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 0x00000017, 4978 TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 0x00000018, 4979 TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 0x00000019, 4980 TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 0x0000001a, 4981 TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 0x0000001b, 4982 TA_PERF_SEL_RESERVED_28 = 0x0000001c, 4983 TA_PERF_SEL_RESERVED_29 = 0x0000001d, 4984 TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e, 4985 TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f, 4986 TA_PERF_SEL_total_wavefronts = 0x00000020, 4987 TA_PERF_SEL_gradient_cycles = 0x00000021, 4988 TA_PERF_SEL_walker_cycles = 0x00000022, 4989 TA_PERF_SEL_aligner_cycles = 0x00000023, 4990 TA_PERF_SEL_image_wavefronts = 0x00000024, 4991 TA_PERF_SEL_image_read_wavefronts = 0x00000025, 4992 TA_PERF_SEL_image_write_wavefronts = 0x00000026, 4993 TA_PERF_SEL_image_atomic_wavefronts = 0x00000027, 4994 TA_PERF_SEL_image_total_cycles = 0x00000028, 4995 TA_PERF_SEL_RESERVED_41 = 0x00000029, 4996 TA_PERF_SEL_RESERVED_42 = 0x0000002a, 4997 TA_PERF_SEL_RESERVED_43 = 0x0000002b, 4998 TA_PERF_SEL_buffer_wavefronts = 0x0000002c, 4999 TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d, 5000 TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e, 5001 TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f, 5002 TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030, 5003 TA_PERF_SEL_buffer_total_cycles = 0x00000031, 5004 TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 0x00000032, 5005 TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 0x00000033, 5006 TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034, 5007 TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035, 5008 TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036, 5009 TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037, 5010 TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038, 5011 TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039, 5012 TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a, 5013 TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b, 5014 TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c, 5015 TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d, 5016 TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e, 5017 TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f, 5018 TA_PERF_SEL_color_1_cycle_pixels = 0x00000040, 5019 TA_PERF_SEL_color_2_cycle_pixels = 0x00000041, 5020 TA_PERF_SEL_color_3_cycle_pixels = 0x00000042, 5021 TA_PERF_SEL_color_4_cycle_pixels = 0x00000043, 5022 TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044, 5023 TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045, 5024 TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046, 5025 TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047, 5026 TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048, 5027 TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049, 5028 TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a, 5029 TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b, 5030 TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c, 5031 TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d, 5032 TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e, 5033 TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f, 5034 TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050, 5035 TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051, 5036 TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052, 5037 TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053, 5038 TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054, 5039 TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055, 5040 TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056, 5041 TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057, 5042 TA_PERF_SEL_mipmap_invalid_samples = 0x00000058, 5043 TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059, 5044 TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a, 5045 TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b, 5046 TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c, 5047 TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d, 5048 TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e, 5049 TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f, 5050 TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060, 5051 TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061, 5052 TA_PERF_SEL_write_path_input_cycles = 0x00000062, 5053 TA_PERF_SEL_write_path_output_cycles = 0x00000063, 5054 TA_PERF_SEL_flat_wavefronts = 0x00000064, 5055 TA_PERF_SEL_flat_read_wavefronts = 0x00000065, 5056 TA_PERF_SEL_flat_write_wavefronts = 0x00000066, 5057 TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067, 5058 TA_PERF_SEL_flat_coalesceable_wavefronts = 0x00000068, 5059 TA_PERF_SEL_reg_sclk_vld = 0x00000069, 5060 TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x0000006a, 5061 TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x0000006b, 5062 TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x0000006c, 5063 TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x0000006d, 5064 TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x0000006e, 5065 TA_PERF_SEL_xnack_on_phase0 = 0x0000006f, 5066 TA_PERF_SEL_xnack_on_phase1 = 0x00000070, 5067 TA_PERF_SEL_xnack_on_phase2 = 0x00000071, 5068 TA_PERF_SEL_xnack_on_phase3 = 0x00000072, 5069 TA_PERF_SEL_first_xnack_on_phase0 = 0x00000073, 5070 TA_PERF_SEL_first_xnack_on_phase1 = 0x00000074, 5071 TA_PERF_SEL_first_xnack_on_phase2 = 0x00000075, 5072 TA_PERF_SEL_first_xnack_on_phase3 = 0x00000076, 5073 } TA_PERFCOUNT_SEL; 5074 5075 /* 5076 * TD_PERFCOUNT_SEL enum 5077 */ 5078 5079 typedef enum TD_PERFCOUNT_SEL { 5080 TD_PERF_SEL_none = 0x00000000, 5081 TD_PERF_SEL_td_busy = 0x00000001, 5082 TD_PERF_SEL_input_busy = 0x00000002, 5083 TD_PERF_SEL_output_busy = 0x00000003, 5084 TD_PERF_SEL_lerp_busy = 0x00000004, 5085 TD_PERF_SEL_reg_sclk_vld = 0x00000005, 5086 TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x00000006, 5087 TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x00000007, 5088 TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x00000008, 5089 TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x00000009, 5090 TD_PERF_SEL_tc_td_fifo_full = 0x0000000a, 5091 TD_PERF_SEL_constant_state_full = 0x0000000b, 5092 TD_PERF_SEL_sample_state_full = 0x0000000c, 5093 TD_PERF_SEL_output_fifo_full = 0x0000000d, 5094 TD_PERF_SEL_RESERVED_14 = 0x0000000e, 5095 TD_PERF_SEL_tc_stall = 0x0000000f, 5096 TD_PERF_SEL_pc_stall = 0x00000010, 5097 TD_PERF_SEL_gds_stall = 0x00000011, 5098 TD_PERF_SEL_RESERVED_18 = 0x00000012, 5099 TD_PERF_SEL_RESERVED_19 = 0x00000013, 5100 TD_PERF_SEL_gather4_wavefront = 0x00000014, 5101 TD_PERF_SEL_gather4h_wavefront = 0x00000015, 5102 TD_PERF_SEL_gather4h_packed_wavefront = 0x00000016, 5103 TD_PERF_SEL_gather8h_packed_wavefront = 0x00000017, 5104 TD_PERF_SEL_sample_c_wavefront = 0x00000018, 5105 TD_PERF_SEL_load_wavefront = 0x00000019, 5106 TD_PERF_SEL_atomic_wavefront = 0x0000001a, 5107 TD_PERF_SEL_store_wavefront = 0x0000001b, 5108 TD_PERF_SEL_ldfptr_wavefront = 0x0000001c, 5109 TD_PERF_SEL_d16_en_wavefront = 0x0000001d, 5110 TD_PERF_SEL_bypass_filter_wavefront = 0x0000001e, 5111 TD_PERF_SEL_min_max_filter_wavefront = 0x0000001f, 5112 TD_PERF_SEL_coalescable_wavefront = 0x00000020, 5113 TD_PERF_SEL_coalesced_phase = 0x00000021, 5114 TD_PERF_SEL_four_phase_wavefront = 0x00000022, 5115 TD_PERF_SEL_eight_phase_wavefront = 0x00000023, 5116 TD_PERF_SEL_sixteen_phase_wavefront = 0x00000024, 5117 TD_PERF_SEL_four_phase_forward_wavefront = 0x00000025, 5118 TD_PERF_SEL_write_ack_wavefront = 0x00000026, 5119 TD_PERF_SEL_RESERVED_39 = 0x00000027, 5120 TD_PERF_SEL_user_defined_border = 0x00000028, 5121 TD_PERF_SEL_white_border = 0x00000029, 5122 TD_PERF_SEL_opaque_black_border = 0x0000002a, 5123 TD_PERF_SEL_RESERVED_43 = 0x0000002b, 5124 TD_PERF_SEL_RESERVED_44 = 0x0000002c, 5125 TD_PERF_SEL_nack = 0x0000002d, 5126 TD_PERF_SEL_td_sp_traffic = 0x0000002e, 5127 TD_PERF_SEL_consume_gds_traffic = 0x0000002f, 5128 TD_PERF_SEL_addresscmd_poison = 0x00000030, 5129 TD_PERF_SEL_data_poison = 0x00000031, 5130 TD_PERF_SEL_start_cycle_0 = 0x00000032, 5131 TD_PERF_SEL_start_cycle_1 = 0x00000033, 5132 TD_PERF_SEL_start_cycle_2 = 0x00000034, 5133 TD_PERF_SEL_start_cycle_3 = 0x00000035, 5134 TD_PERF_SEL_null_cycle_output = 0x00000036, 5135 TD_PERF_SEL_d16_data_packed = 0x00000037, 5136 TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 0x00000038, 5137 } TD_PERFCOUNT_SEL; 5138 5139 /* 5140 * TCP_PERFCOUNT_SELECT enum 5141 */ 5142 5143 typedef enum TCP_PERFCOUNT_SELECT { 5144 TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x00000000, 5145 TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x00000001, 5146 TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x00000002, 5147 TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x00000003, 5148 TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x00000004, 5149 TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x00000005, 5150 TCP_PERF_SEL_LOD_STALL_CYCLES = 0x00000006, 5151 TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x00000007, 5152 TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x00000008, 5153 TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x00000009, 5154 TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0x0000000a, 5155 TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0x0000000b, 5156 TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0x0000000c, 5157 TCP_PERF_SEL_TCR_RDRET_STALL = 0x0000000d, 5158 TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0x0000000e, 5159 TCP_PERF_SEL_HOLE_READ_STALL = 0x0000000f, 5160 TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x00000010, 5161 TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x00000011, 5162 TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x00000012, 5163 TCP_PERF_SEL_TCP_LATENCY = 0x00000013, 5164 TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x00000014, 5165 TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x00000015, 5166 TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x00000016, 5167 TCP_PERF_SEL_TCC_READ_REQ = 0x00000017, 5168 TCP_PERF_SEL_TCC_WRITE_REQ = 0x00000018, 5169 TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x00000019, 5170 TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x0000001a, 5171 TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x0000001b, 5172 TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x0000001c, 5173 TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x0000001d, 5174 TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x0000001e, 5175 TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x0000001f, 5176 TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x00000020, 5177 TCP_PERF_SEL_TOTAL_WBINVL1 = 0x00000021, 5178 TCP_PERF_SEL_IMG_READ_FMT_1 = 0x00000022, 5179 TCP_PERF_SEL_IMG_READ_FMT_8 = 0x00000023, 5180 TCP_PERF_SEL_IMG_READ_FMT_16 = 0x00000024, 5181 TCP_PERF_SEL_IMG_READ_FMT_32 = 0x00000025, 5182 TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x00000026, 5183 TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x00000027, 5184 TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x00000028, 5185 TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x00000029, 5186 TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x0000002a, 5187 TCP_PERF_SEL_IMG_READ_FMT_96 = 0x0000002b, 5188 TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x0000002c, 5189 TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x0000002d, 5190 TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x0000002e, 5191 TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x0000002f, 5192 TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x00000030, 5193 TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x00000031, 5194 TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x00000032, 5195 TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x00000033, 5196 TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x00000034, 5197 TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x00000035, 5198 TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x00000036, 5199 TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x00000037, 5200 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x00000038, 5201 TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x00000039, 5202 TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x0000003a, 5203 TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x0000003b, 5204 TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x0000003c, 5205 TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x0000003d, 5206 TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x0000003e, 5207 TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x0000003f, 5208 TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x00000040, 5209 TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x00000041, 5210 TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x00000042, 5211 TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x00000043, 5212 TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x00000044, 5213 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x00000045, 5214 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000046, 5215 TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x00000047, 5216 TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000048, 5217 TCP_PERF_SEL_BUF_READ_FMT_8 = 0x00000049, 5218 TCP_PERF_SEL_BUF_READ_FMT_16 = 0x0000004a, 5219 TCP_PERF_SEL_BUF_READ_FMT_32 = 0x0000004b, 5220 TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x0000004c, 5221 TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x0000004d, 5222 TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x0000004e, 5223 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x0000004f, 5224 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x00000050, 5225 TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x00000051, 5226 TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x00000052, 5227 TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x00000053, 5228 TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x00000054, 5229 TCP_PERF_SEL_ARR_1D_THIN1 = 0x00000055, 5230 TCP_PERF_SEL_ARR_1D_THICK = 0x00000056, 5231 TCP_PERF_SEL_ARR_2D_THIN1 = 0x00000057, 5232 TCP_PERF_SEL_ARR_2D_THICK = 0x00000058, 5233 TCP_PERF_SEL_ARR_2D_XTHICK = 0x00000059, 5234 TCP_PERF_SEL_ARR_3D_THIN1 = 0x0000005a, 5235 TCP_PERF_SEL_ARR_3D_THICK = 0x0000005b, 5236 TCP_PERF_SEL_ARR_3D_XTHICK = 0x0000005c, 5237 TCP_PERF_SEL_DIM_1D = 0x0000005d, 5238 TCP_PERF_SEL_DIM_2D = 0x0000005e, 5239 TCP_PERF_SEL_DIM_3D = 0x0000005f, 5240 TCP_PERF_SEL_DIM_1D_ARRAY = 0x00000060, 5241 TCP_PERF_SEL_DIM_2D_ARRAY = 0x00000061, 5242 TCP_PERF_SEL_DIM_2D_MSAA = 0x00000062, 5243 TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x00000063, 5244 TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x00000064, 5245 TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x00000065, 5246 TCP_PERF_SEL_TA_TCP_STATE_READ = 0x00000066, 5247 TCP_PERF_SEL_TAGRAM0_REQ = 0x00000067, 5248 TCP_PERF_SEL_TAGRAM1_REQ = 0x00000068, 5249 TCP_PERF_SEL_TAGRAM2_REQ = 0x00000069, 5250 TCP_PERF_SEL_TAGRAM3_REQ = 0x0000006a, 5251 TCP_PERF_SEL_GATE_EN1 = 0x0000006b, 5252 TCP_PERF_SEL_GATE_EN2 = 0x0000006c, 5253 TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x0000006d, 5254 TCP_PERF_SEL_TCC_REQ = 0x0000006e, 5255 TCP_PERF_SEL_TCC_NON_READ_REQ = 0x0000006f, 5256 TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x00000070, 5257 TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x00000071, 5258 TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x00000072, 5259 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x00000073, 5260 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x00000074, 5261 TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x00000075, 5262 TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x00000076, 5263 TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x00000077, 5264 TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x00000078, 5265 TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x00000079, 5266 TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x0000007a, 5267 TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x0000007b, 5268 TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x0000007c, 5269 TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x0000007d, 5270 TCP_PERF_SEL_TOTAL_ACCESSES = 0x0000007e, 5271 TCP_PERF_SEL_TOTAL_READ = 0x0000007f, 5272 TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x00000080, 5273 TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x00000081, 5274 TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x00000082, 5275 TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x00000083, 5276 TCP_PERF_SEL_TOTAL_NON_READ = 0x00000084, 5277 TCP_PERF_SEL_TOTAL_WRITE = 0x00000085, 5278 TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x00000086, 5279 TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x00000087, 5280 TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x00000088, 5281 TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x00000089, 5282 TCP_PERF_SEL_DISPLAY_MICROTILING = 0x0000008a, 5283 TCP_PERF_SEL_THIN_MICROTILING = 0x0000008b, 5284 TCP_PERF_SEL_DEPTH_MICROTILING = 0x0000008c, 5285 TCP_PERF_SEL_ARR_PRT_THIN1 = 0x0000008d, 5286 TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x0000008e, 5287 TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x0000008f, 5288 TCP_PERF_SEL_ARR_PRT_THICK = 0x00000090, 5289 TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x00000091, 5290 TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x00000092, 5291 TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x00000093, 5292 TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x00000094, 5293 TCP_PERF_SEL_UNALIGNED = 0x00000095, 5294 TCP_PERF_SEL_ROTATED_MICROTILING = 0x00000096, 5295 TCP_PERF_SEL_THICK_MICROTILING = 0x00000097, 5296 TCP_PERF_SEL_ATC = 0x00000098, 5297 TCP_PERF_SEL_POWER_STALL = 0x00000099, 5298 TCP_PERF_SEL_RESERVED_154 = 0x0000009a, 5299 TCP_PERF_SEL_TCC_LRU_REQ = 0x0000009b, 5300 TCP_PERF_SEL_TCC_STREAM_REQ = 0x0000009c, 5301 TCP_PERF_SEL_TCC_NC_READ_REQ = 0x0000009d, 5302 TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x0000009e, 5303 TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x0000009f, 5304 TCP_PERF_SEL_TCC_UC_READ_REQ = 0x000000a0, 5305 TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0x000000a1, 5306 TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0x000000a2, 5307 TCP_PERF_SEL_TCC_CC_READ_REQ = 0x000000a3, 5308 TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0x000000a4, 5309 TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0x000000a5, 5310 TCP_PERF_SEL_TCC_DCC_REQ = 0x000000a6, 5311 TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0x000000a7, 5312 TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x000000a8, 5313 TCP_PERF_SEL_VOLATILE = 0x000000a9, 5314 TCP_PERF_SEL_TC_TA_XNACK_STALL = 0x000000aa, 5315 TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 0x000000ab, 5316 TCP_PERF_SEL_SHOOTDOWN = 0x000000ac, 5317 TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x000000ad, 5318 TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 0x000000ae, 5319 TCP_PERF_SEL_UTCL1_REQUEST = 0x000000af, 5320 TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x000000b0, 5321 TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x000000b1, 5322 TCP_PERF_SEL_UTCL1_LFIFO_FULL = 0x000000b2, 5323 TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x000000b3, 5324 TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x000000b4, 5325 TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 0x000000b5, 5326 TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x000000b6, 5327 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 0x000000b7, 5328 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 0x000000b8, 5329 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 0x000000b9, 5330 TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 0x000000ba, 5331 TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 0x000000bb, 5332 TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 0x000000bc, 5333 TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 0x000000bd, 5334 TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 0x000000be, 5335 TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 0x000000bf, 5336 TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 0x000000c0, 5337 TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 0x000000c1, 5338 TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 0x000000c2, 5339 TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 0x000000c3, 5340 } TCP_PERFCOUNT_SELECT; 5341 5342 /* 5343 * TCP_CACHE_POLICIES enum 5344 */ 5345 5346 typedef enum TCP_CACHE_POLICIES { 5347 TCP_CACHE_POLICY_MISS_LRU = 0x00000000, 5348 TCP_CACHE_POLICY_MISS_EVICT = 0x00000001, 5349 TCP_CACHE_POLICY_HIT_LRU = 0x00000002, 5350 TCP_CACHE_POLICY_HIT_EVICT = 0x00000003, 5351 } TCP_CACHE_POLICIES; 5352 5353 /* 5354 * TCP_CACHE_STORE_POLICIES enum 5355 */ 5356 5357 typedef enum TCP_CACHE_STORE_POLICIES { 5358 TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000, 5359 TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001, 5360 } TCP_CACHE_STORE_POLICIES; 5361 5362 /* 5363 * TCP_WATCH_MODES enum 5364 */ 5365 5366 typedef enum TCP_WATCH_MODES { 5367 TCP_WATCH_MODE_READ = 0x00000000, 5368 TCP_WATCH_MODE_NONREAD = 0x00000001, 5369 TCP_WATCH_MODE_ATOMIC = 0x00000002, 5370 TCP_WATCH_MODE_ALL = 0x00000003, 5371 } TCP_WATCH_MODES; 5372 5373 /* 5374 * TCP_DSM_DATA_SEL enum 5375 */ 5376 5377 typedef enum TCP_DSM_DATA_SEL { 5378 TCP_DSM_DISABLE = 0x00000000, 5379 TCP_DSM_SEL0 = 0x00000001, 5380 TCP_DSM_SEL1 = 0x00000002, 5381 TCP_DSM_SEL_BOTH = 0x00000003, 5382 } TCP_DSM_DATA_SEL; 5383 5384 /* 5385 * TCP_DSM_SINGLE_WRITE enum 5386 */ 5387 5388 typedef enum TCP_DSM_SINGLE_WRITE { 5389 TCP_DSM_SINGLE_WRITE_DIS = 0x00000000, 5390 TCP_DSM_SINGLE_WRITE_EN = 0x00000001, 5391 } TCP_DSM_SINGLE_WRITE; 5392 5393 /* 5394 * TCP_DSM_INJECT_SEL enum 5395 */ 5396 5397 typedef enum TCP_DSM_INJECT_SEL { 5398 TCP_DSM_INJECT_SEL0 = 0x00000000, 5399 TCP_DSM_INJECT_SEL1 = 0x00000001, 5400 TCP_DSM_INJECT_SEL2 = 0x00000002, 5401 TCP_DSM_INJECT_SEL3 = 0x00000003, 5402 } TCP_DSM_INJECT_SEL; 5403 5404 /******************************************************* 5405 * TCC Enums 5406 *******************************************************/ 5407 5408 /* 5409 * TCC_PERF_SEL enum 5410 */ 5411 5412 typedef enum TCC_PERF_SEL { 5413 TCC_PERF_SEL_NONE = 0x00000000, 5414 TCC_PERF_SEL_CYCLE = 0x00000001, 5415 TCC_PERF_SEL_BUSY = 0x00000002, 5416 TCC_PERF_SEL_REQ = 0x00000003, 5417 TCC_PERF_SEL_STREAMING_REQ = 0x00000004, 5418 TCC_PERF_SEL_EXE_REQ = 0x00000005, 5419 TCC_PERF_SEL_COMPRESSED_REQ = 0x00000006, 5420 TCC_PERF_SEL_COMPRESSED_0_REQ = 0x00000007, 5421 TCC_PERF_SEL_METADATA_REQ = 0x00000008, 5422 TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x00000009, 5423 TCC_PERF_SEL_UC_VIRTUAL_REQ = 0x0000000a, 5424 TCC_PERF_SEL_CC_PHYSICAL_REQ = 0x0000000b, 5425 TCC_PERF_SEL_PROBE = 0x0000000c, 5426 TCC_PERF_SEL_PROBE_ALL = 0x0000000d, 5427 TCC_PERF_SEL_READ = 0x0000000e, 5428 TCC_PERF_SEL_WRITE = 0x0000000f, 5429 TCC_PERF_SEL_ATOMIC = 0x00000010, 5430 TCC_PERF_SEL_HIT = 0x00000011, 5431 TCC_PERF_SEL_SECTOR_HIT = 0x00000012, 5432 TCC_PERF_SEL_MISS = 0x00000013, 5433 TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000014, 5434 TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000015, 5435 TCC_PERF_SEL_WRITEBACK = 0x00000016, 5436 TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x00000017, 5437 TCC_PERF_SEL_SRC_FIFO_FULL = 0x00000018, 5438 TCC_PERF_SEL_HOLE_FIFO_FULL = 0x00000019, 5439 TCC_PERF_SEL_EA_WRREQ = 0x0000001a, 5440 TCC_PERF_SEL_EA_WRREQ_64B = 0x0000001b, 5441 TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x0000001c, 5442 TCC_PERF_SEL_EA_WR_UNCACHED_32B = 0x0000001d, 5443 TCC_PERF_SEL_EA_WRREQ_STALL = 0x0000001e, 5444 TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL = 0x0000001f, 5445 TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x00000020, 5446 TCC_PERF_SEL_EA_WRREQ_LEVEL = 0x00000021, 5447 TCC_PERF_SEL_EA_ATOMIC = 0x00000022, 5448 TCC_PERF_SEL_EA_ATOMIC_LEVEL = 0x00000023, 5449 TCC_PERF_SEL_EA_RDREQ = 0x00000024, 5450 TCC_PERF_SEL_EA_RDREQ_32B = 0x00000025, 5451 TCC_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000026, 5452 TCC_PERF_SEL_EA_RD_MDC_32B = 0x00000027, 5453 TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000028, 5454 TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL = 0x00000029, 5455 TCC_PERF_SEL_EA_RDREQ_LEVEL = 0x0000002a, 5456 TCC_PERF_SEL_TAG_STALL = 0x0000002b, 5457 TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000002c, 5458 TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000002d, 5459 TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000002e, 5460 TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000002f, 5461 TCC_PERF_SEL_TAG_PROBE_STALL = 0x00000030, 5462 TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000031, 5463 TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000032, 5464 TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000033, 5465 TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000034, 5466 TCC_PERF_SEL_BUBBLE = 0x00000035, 5467 TCC_PERF_SEL_RETURN_ACK = 0x00000036, 5468 TCC_PERF_SEL_RETURN_DATA = 0x00000037, 5469 TCC_PERF_SEL_RETURN_HOLE = 0x00000038, 5470 TCC_PERF_SEL_RETURN_ACK_HOLE = 0x00000039, 5471 TCC_PERF_SEL_IB_REQ = 0x0000003a, 5472 TCC_PERF_SEL_IB_STALL = 0x0000003b, 5473 TCC_PERF_SEL_IB_TAG_STALL = 0x0000003c, 5474 TCC_PERF_SEL_IB_MDC_STALL = 0x0000003d, 5475 TCC_PERF_SEL_TCA_LEVEL = 0x0000003e, 5476 TCC_PERF_SEL_HOLE_LEVEL = 0x0000003f, 5477 TCC_PERF_SEL_EA_RDRET_NACK = 0x00000040, 5478 TCC_PERF_SEL_EA_WRRET_NACK = 0x00000041, 5479 TCC_PERF_SEL_NORMAL_WRITEBACK = 0x00000042, 5480 TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x00000043, 5481 TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK = 0x00000044, 5482 TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x00000045, 5483 TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x00000046, 5484 TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x00000047, 5485 TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x00000048, 5486 TCC_PERF_SEL_NORMAL_EVICT = 0x00000049, 5487 TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x0000004a, 5488 TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT = 0x0000004b, 5489 TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x0000004c, 5490 TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x0000004d, 5491 TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x0000004e, 5492 TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x0000004f, 5493 TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x00000050, 5494 TCC_PERF_SEL_PROBE_EVICT = 0x00000051, 5495 TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x00000052, 5496 TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE = 0x00000053, 5497 TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x00000054, 5498 TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x00000055, 5499 TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x00000056, 5500 TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x00000057, 5501 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x00000058, 5502 TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x00000059, 5503 TCC_PERF_SEL_TC_OP_WBL2_WC_START = 0x0000005a, 5504 TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x0000005b, 5505 TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x0000005c, 5506 TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x0000005d, 5507 TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x0000005e, 5508 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x0000005f, 5509 TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x00000060, 5510 TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH = 0x00000061, 5511 TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x00000062, 5512 TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x00000063, 5513 TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x00000064, 5514 TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x00000065, 5515 TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x00000066, 5516 TCC_PERF_SEL_MDC_REQ = 0x00000067, 5517 TCC_PERF_SEL_MDC_LEVEL = 0x00000068, 5518 TCC_PERF_SEL_MDC_TAG_HIT = 0x00000069, 5519 TCC_PERF_SEL_MDC_SECTOR_HIT = 0x0000006a, 5520 TCC_PERF_SEL_MDC_SECTOR_MISS = 0x0000006b, 5521 TCC_PERF_SEL_MDC_TAG_STALL = 0x0000006c, 5522 TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x0000006d, 5523 TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x0000006e, 5524 TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x0000006f, 5525 TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000070, 5526 TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x00000071, 5527 TCC_PERF_SEL_CLIENT0_REQ = 0x00000080, 5528 TCC_PERF_SEL_CLIENT1_REQ = 0x00000081, 5529 TCC_PERF_SEL_CLIENT2_REQ = 0x00000082, 5530 TCC_PERF_SEL_CLIENT3_REQ = 0x00000083, 5531 TCC_PERF_SEL_CLIENT4_REQ = 0x00000084, 5532 TCC_PERF_SEL_CLIENT5_REQ = 0x00000085, 5533 TCC_PERF_SEL_CLIENT6_REQ = 0x00000086, 5534 TCC_PERF_SEL_CLIENT7_REQ = 0x00000087, 5535 TCC_PERF_SEL_CLIENT8_REQ = 0x00000088, 5536 TCC_PERF_SEL_CLIENT9_REQ = 0x00000089, 5537 TCC_PERF_SEL_CLIENT10_REQ = 0x0000008a, 5538 TCC_PERF_SEL_CLIENT11_REQ = 0x0000008b, 5539 TCC_PERF_SEL_CLIENT12_REQ = 0x0000008c, 5540 TCC_PERF_SEL_CLIENT13_REQ = 0x0000008d, 5541 TCC_PERF_SEL_CLIENT14_REQ = 0x0000008e, 5542 TCC_PERF_SEL_CLIENT15_REQ = 0x0000008f, 5543 TCC_PERF_SEL_CLIENT16_REQ = 0x00000090, 5544 TCC_PERF_SEL_CLIENT17_REQ = 0x00000091, 5545 TCC_PERF_SEL_CLIENT18_REQ = 0x00000092, 5546 TCC_PERF_SEL_CLIENT19_REQ = 0x00000093, 5547 TCC_PERF_SEL_CLIENT20_REQ = 0x00000094, 5548 TCC_PERF_SEL_CLIENT21_REQ = 0x00000095, 5549 TCC_PERF_SEL_CLIENT22_REQ = 0x00000096, 5550 TCC_PERF_SEL_CLIENT23_REQ = 0x00000097, 5551 TCC_PERF_SEL_CLIENT24_REQ = 0x00000098, 5552 TCC_PERF_SEL_CLIENT25_REQ = 0x00000099, 5553 TCC_PERF_SEL_CLIENT26_REQ = 0x0000009a, 5554 TCC_PERF_SEL_CLIENT27_REQ = 0x0000009b, 5555 TCC_PERF_SEL_CLIENT28_REQ = 0x0000009c, 5556 TCC_PERF_SEL_CLIENT29_REQ = 0x0000009d, 5557 TCC_PERF_SEL_CLIENT30_REQ = 0x0000009e, 5558 TCC_PERF_SEL_CLIENT31_REQ = 0x0000009f, 5559 TCC_PERF_SEL_CLIENT32_REQ = 0x000000a0, 5560 TCC_PERF_SEL_CLIENT33_REQ = 0x000000a1, 5561 TCC_PERF_SEL_CLIENT34_REQ = 0x000000a2, 5562 TCC_PERF_SEL_CLIENT35_REQ = 0x000000a3, 5563 TCC_PERF_SEL_CLIENT36_REQ = 0x000000a4, 5564 TCC_PERF_SEL_CLIENT37_REQ = 0x000000a5, 5565 TCC_PERF_SEL_CLIENT38_REQ = 0x000000a6, 5566 TCC_PERF_SEL_CLIENT39_REQ = 0x000000a7, 5567 TCC_PERF_SEL_CLIENT40_REQ = 0x000000a8, 5568 TCC_PERF_SEL_CLIENT41_REQ = 0x000000a9, 5569 TCC_PERF_SEL_CLIENT42_REQ = 0x000000aa, 5570 TCC_PERF_SEL_CLIENT43_REQ = 0x000000ab, 5571 TCC_PERF_SEL_CLIENT44_REQ = 0x000000ac, 5572 TCC_PERF_SEL_CLIENT45_REQ = 0x000000ad, 5573 TCC_PERF_SEL_CLIENT46_REQ = 0x000000ae, 5574 TCC_PERF_SEL_CLIENT47_REQ = 0x000000af, 5575 TCC_PERF_SEL_CLIENT48_REQ = 0x000000b0, 5576 TCC_PERF_SEL_CLIENT49_REQ = 0x000000b1, 5577 TCC_PERF_SEL_CLIENT50_REQ = 0x000000b2, 5578 TCC_PERF_SEL_CLIENT51_REQ = 0x000000b3, 5579 TCC_PERF_SEL_CLIENT52_REQ = 0x000000b4, 5580 TCC_PERF_SEL_CLIENT53_REQ = 0x000000b5, 5581 TCC_PERF_SEL_CLIENT54_REQ = 0x000000b6, 5582 TCC_PERF_SEL_CLIENT55_REQ = 0x000000b7, 5583 TCC_PERF_SEL_CLIENT56_REQ = 0x000000b8, 5584 TCC_PERF_SEL_CLIENT57_REQ = 0x000000b9, 5585 TCC_PERF_SEL_CLIENT58_REQ = 0x000000ba, 5586 TCC_PERF_SEL_CLIENT59_REQ = 0x000000bb, 5587 TCC_PERF_SEL_CLIENT60_REQ = 0x000000bc, 5588 TCC_PERF_SEL_CLIENT61_REQ = 0x000000bd, 5589 TCC_PERF_SEL_CLIENT62_REQ = 0x000000be, 5590 TCC_PERF_SEL_CLIENT63_REQ = 0x000000bf, 5591 TCC_PERF_SEL_CLIENT64_REQ = 0x000000c0, 5592 TCC_PERF_SEL_CLIENT65_REQ = 0x000000c1, 5593 TCC_PERF_SEL_CLIENT66_REQ = 0x000000c2, 5594 TCC_PERF_SEL_CLIENT67_REQ = 0x000000c3, 5595 TCC_PERF_SEL_CLIENT68_REQ = 0x000000c4, 5596 TCC_PERF_SEL_CLIENT69_REQ = 0x000000c5, 5597 TCC_PERF_SEL_CLIENT70_REQ = 0x000000c6, 5598 TCC_PERF_SEL_CLIENT71_REQ = 0x000000c7, 5599 TCC_PERF_SEL_CLIENT72_REQ = 0x000000c8, 5600 TCC_PERF_SEL_CLIENT73_REQ = 0x000000c9, 5601 TCC_PERF_SEL_CLIENT74_REQ = 0x000000ca, 5602 TCC_PERF_SEL_CLIENT75_REQ = 0x000000cb, 5603 TCC_PERF_SEL_CLIENT76_REQ = 0x000000cc, 5604 TCC_PERF_SEL_CLIENT77_REQ = 0x000000cd, 5605 TCC_PERF_SEL_CLIENT78_REQ = 0x000000ce, 5606 TCC_PERF_SEL_CLIENT79_REQ = 0x000000cf, 5607 TCC_PERF_SEL_CLIENT80_REQ = 0x000000d0, 5608 TCC_PERF_SEL_CLIENT81_REQ = 0x000000d1, 5609 TCC_PERF_SEL_CLIENT82_REQ = 0x000000d2, 5610 TCC_PERF_SEL_CLIENT83_REQ = 0x000000d3, 5611 TCC_PERF_SEL_CLIENT84_REQ = 0x000000d4, 5612 TCC_PERF_SEL_CLIENT85_REQ = 0x000000d5, 5613 TCC_PERF_SEL_CLIENT86_REQ = 0x000000d6, 5614 TCC_PERF_SEL_CLIENT87_REQ = 0x000000d7, 5615 TCC_PERF_SEL_CLIENT88_REQ = 0x000000d8, 5616 TCC_PERF_SEL_CLIENT89_REQ = 0x000000d9, 5617 TCC_PERF_SEL_CLIENT90_REQ = 0x000000da, 5618 TCC_PERF_SEL_CLIENT91_REQ = 0x000000db, 5619 TCC_PERF_SEL_CLIENT92_REQ = 0x000000dc, 5620 TCC_PERF_SEL_CLIENT93_REQ = 0x000000dd, 5621 TCC_PERF_SEL_CLIENT94_REQ = 0x000000de, 5622 TCC_PERF_SEL_CLIENT95_REQ = 0x000000df, 5623 TCC_PERF_SEL_CLIENT96_REQ = 0x000000e0, 5624 TCC_PERF_SEL_CLIENT97_REQ = 0x000000e1, 5625 TCC_PERF_SEL_CLIENT98_REQ = 0x000000e2, 5626 TCC_PERF_SEL_CLIENT99_REQ = 0x000000e3, 5627 TCC_PERF_SEL_CLIENT100_REQ = 0x000000e4, 5628 TCC_PERF_SEL_CLIENT101_REQ = 0x000000e5, 5629 TCC_PERF_SEL_CLIENT102_REQ = 0x000000e6, 5630 TCC_PERF_SEL_CLIENT103_REQ = 0x000000e7, 5631 TCC_PERF_SEL_CLIENT104_REQ = 0x000000e8, 5632 TCC_PERF_SEL_CLIENT105_REQ = 0x000000e9, 5633 TCC_PERF_SEL_CLIENT106_REQ = 0x000000ea, 5634 TCC_PERF_SEL_CLIENT107_REQ = 0x000000eb, 5635 TCC_PERF_SEL_CLIENT108_REQ = 0x000000ec, 5636 TCC_PERF_SEL_CLIENT109_REQ = 0x000000ed, 5637 TCC_PERF_SEL_CLIENT110_REQ = 0x000000ee, 5638 TCC_PERF_SEL_CLIENT111_REQ = 0x000000ef, 5639 TCC_PERF_SEL_CLIENT112_REQ = 0x000000f0, 5640 TCC_PERF_SEL_CLIENT113_REQ = 0x000000f1, 5641 TCC_PERF_SEL_CLIENT114_REQ = 0x000000f2, 5642 TCC_PERF_SEL_CLIENT115_REQ = 0x000000f3, 5643 TCC_PERF_SEL_CLIENT116_REQ = 0x000000f4, 5644 TCC_PERF_SEL_CLIENT117_REQ = 0x000000f5, 5645 TCC_PERF_SEL_CLIENT118_REQ = 0x000000f6, 5646 TCC_PERF_SEL_CLIENT119_REQ = 0x000000f7, 5647 TCC_PERF_SEL_CLIENT120_REQ = 0x000000f8, 5648 TCC_PERF_SEL_CLIENT121_REQ = 0x000000f9, 5649 TCC_PERF_SEL_CLIENT122_REQ = 0x000000fa, 5650 TCC_PERF_SEL_CLIENT123_REQ = 0x000000fb, 5651 TCC_PERF_SEL_CLIENT124_REQ = 0x000000fc, 5652 TCC_PERF_SEL_CLIENT125_REQ = 0x000000fd, 5653 TCC_PERF_SEL_CLIENT126_REQ = 0x000000fe, 5654 TCC_PERF_SEL_CLIENT127_REQ = 0x000000ff, 5655 } TCC_PERF_SEL; 5656 5657 /* 5658 * TCA_PERF_SEL enum 5659 */ 5660 5661 typedef enum TCA_PERF_SEL { 5662 TCA_PERF_SEL_NONE = 0x00000000, 5663 TCA_PERF_SEL_CYCLE = 0x00000001, 5664 TCA_PERF_SEL_BUSY = 0x00000002, 5665 TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x00000003, 5666 TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x00000004, 5667 TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x00000005, 5668 TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x00000006, 5669 TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x00000007, 5670 TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x00000008, 5671 TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x00000009, 5672 TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0x0000000a, 5673 TCA_PERF_SEL_REQ_TCC0 = 0x0000000b, 5674 TCA_PERF_SEL_REQ_TCC1 = 0x0000000c, 5675 TCA_PERF_SEL_REQ_TCC2 = 0x0000000d, 5676 TCA_PERF_SEL_REQ_TCC3 = 0x0000000e, 5677 TCA_PERF_SEL_REQ_TCC4 = 0x0000000f, 5678 TCA_PERF_SEL_REQ_TCC5 = 0x00000010, 5679 TCA_PERF_SEL_REQ_TCC6 = 0x00000011, 5680 TCA_PERF_SEL_REQ_TCC7 = 0x00000012, 5681 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x00000013, 5682 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x00000014, 5683 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x00000015, 5684 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x00000016, 5685 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x00000017, 5686 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x00000018, 5687 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x00000019, 5688 TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x0000001a, 5689 TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x0000001b, 5690 TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x0000001c, 5691 TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x0000001d, 5692 TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x0000001e, 5693 TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x0000001f, 5694 TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x00000020, 5695 TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x00000021, 5696 TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x00000022, 5697 } TCA_PERF_SEL; 5698 5699 /******************************************************* 5700 * GRBM Enums 5701 *******************************************************/ 5702 5703 /* 5704 * GRBM_PERF_SEL enum 5705 */ 5706 5707 typedef enum GRBM_PERF_SEL { 5708 GRBM_PERF_SEL_COUNT = 0x00000000, 5709 GRBM_PERF_SEL_USER_DEFINED = 0x00000001, 5710 GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002, 5711 GRBM_PERF_SEL_CP_BUSY = 0x00000003, 5712 GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004, 5713 GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005, 5714 GRBM_PERF_SEL_CB_BUSY = 0x00000006, 5715 GRBM_PERF_SEL_DB_BUSY = 0x00000007, 5716 GRBM_PERF_SEL_PA_BUSY = 0x00000008, 5717 GRBM_PERF_SEL_SC_BUSY = 0x00000009, 5718 GRBM_PERF_SEL_RESERVED_6 = 0x0000000a, 5719 GRBM_PERF_SEL_SPI_BUSY = 0x0000000b, 5720 GRBM_PERF_SEL_SX_BUSY = 0x0000000c, 5721 GRBM_PERF_SEL_TA_BUSY = 0x0000000d, 5722 GRBM_PERF_SEL_CB_CLEAN = 0x0000000e, 5723 GRBM_PERF_SEL_DB_CLEAN = 0x0000000f, 5724 GRBM_PERF_SEL_RESERVED_5 = 0x00000010, 5725 GRBM_PERF_SEL_VGT_BUSY = 0x00000011, 5726 GRBM_PERF_SEL_RESERVED_4 = 0x00000012, 5727 GRBM_PERF_SEL_RESERVED_3 = 0x00000013, 5728 GRBM_PERF_SEL_RESERVED_2 = 0x00000014, 5729 GRBM_PERF_SEL_RESERVED_1 = 0x00000015, 5730 GRBM_PERF_SEL_RESERVED_0 = 0x00000016, 5731 GRBM_PERF_SEL_IA_BUSY = 0x00000017, 5732 GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x00000018, 5733 GRBM_PERF_SEL_GDS_BUSY = 0x00000019, 5734 GRBM_PERF_SEL_BCI_BUSY = 0x0000001a, 5735 GRBM_PERF_SEL_RLC_BUSY = 0x0000001b, 5736 GRBM_PERF_SEL_TC_BUSY = 0x0000001c, 5737 GRBM_PERF_SEL_CPG_BUSY = 0x0000001d, 5738 GRBM_PERF_SEL_CPC_BUSY = 0x0000001e, 5739 GRBM_PERF_SEL_CPF_BUSY = 0x0000001f, 5740 GRBM_PERF_SEL_WD_BUSY = 0x00000020, 5741 GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x00000021, 5742 GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022, 5743 GRBM_PERF_SEL_EA_BUSY = 0x00000023, 5744 GRBM_PERF_SEL_RMI_BUSY = 0x00000024, 5745 GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025, 5746 } GRBM_PERF_SEL; 5747 5748 /* 5749 * GRBM_SE0_PERF_SEL enum 5750 */ 5751 5752 typedef enum GRBM_SE0_PERF_SEL { 5753 GRBM_SE0_PERF_SEL_COUNT = 0x00000000, 5754 GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001, 5755 GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002, 5756 GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003, 5757 GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004, 5758 GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005, 5759 GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006, 5760 GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007, 5761 GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008, 5762 GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009, 5763 GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a, 5764 GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b, 5765 GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c, 5766 GRBM_SE0_PERF_SEL_VGT_BUSY = 0x0000000d, 5767 GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e, 5768 GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f, 5769 } GRBM_SE0_PERF_SEL; 5770 5771 /* 5772 * GRBM_SE1_PERF_SEL enum 5773 */ 5774 5775 typedef enum GRBM_SE1_PERF_SEL { 5776 GRBM_SE1_PERF_SEL_COUNT = 0x00000000, 5777 GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001, 5778 GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002, 5779 GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003, 5780 GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004, 5781 GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005, 5782 GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006, 5783 GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007, 5784 GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008, 5785 GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009, 5786 GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a, 5787 GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b, 5788 GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c, 5789 GRBM_SE1_PERF_SEL_VGT_BUSY = 0x0000000d, 5790 GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e, 5791 GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f, 5792 } GRBM_SE1_PERF_SEL; 5793 5794 /* 5795 * GRBM_SE2_PERF_SEL enum 5796 */ 5797 5798 typedef enum GRBM_SE2_PERF_SEL { 5799 GRBM_SE2_PERF_SEL_COUNT = 0x00000000, 5800 GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001, 5801 GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002, 5802 GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003, 5803 GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004, 5804 GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005, 5805 GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006, 5806 GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007, 5807 GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008, 5808 GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009, 5809 GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a, 5810 GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b, 5811 GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c, 5812 GRBM_SE2_PERF_SEL_VGT_BUSY = 0x0000000d, 5813 GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e, 5814 GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f, 5815 } GRBM_SE2_PERF_SEL; 5816 5817 /* 5818 * GRBM_SE3_PERF_SEL enum 5819 */ 5820 5821 typedef enum GRBM_SE3_PERF_SEL { 5822 GRBM_SE3_PERF_SEL_COUNT = 0x00000000, 5823 GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001, 5824 GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002, 5825 GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003, 5826 GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004, 5827 GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005, 5828 GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006, 5829 GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007, 5830 GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008, 5831 GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009, 5832 GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a, 5833 GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b, 5834 GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c, 5835 GRBM_SE3_PERF_SEL_VGT_BUSY = 0x0000000d, 5836 GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e, 5837 GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f, 5838 } GRBM_SE3_PERF_SEL; 5839 5840 /******************************************************* 5841 * CP Enums 5842 *******************************************************/ 5843 5844 /* 5845 * CP_RING_ID enum 5846 */ 5847 5848 typedef enum CP_RING_ID { 5849 RINGID0 = 0x00000000, 5850 RINGID1 = 0x00000001, 5851 RINGID2 = 0x00000002, 5852 RINGID3 = 0x00000003, 5853 } CP_RING_ID; 5854 5855 /* 5856 * CP_PIPE_ID enum 5857 */ 5858 5859 typedef enum CP_PIPE_ID { 5860 PIPE_ID0 = 0x00000000, 5861 PIPE_ID1 = 0x00000001, 5862 PIPE_ID2 = 0x00000002, 5863 PIPE_ID3 = 0x00000003, 5864 } CP_PIPE_ID; 5865 5866 /* 5867 * CP_ME_ID enum 5868 */ 5869 5870 typedef enum CP_ME_ID { 5871 ME_ID0 = 0x00000000, 5872 ME_ID1 = 0x00000001, 5873 ME_ID2 = 0x00000002, 5874 ME_ID3 = 0x00000003, 5875 } CP_ME_ID; 5876 5877 /* 5878 * SPM_PERFMON_STATE enum 5879 */ 5880 5881 typedef enum SPM_PERFMON_STATE { 5882 STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, 5883 STRM_PERFMON_STATE_START_COUNTING = 0x00000001, 5884 STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002, 5885 STRM_PERFMON_STATE_RESERVED_3 = 0x00000003, 5886 STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, 5887 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, 5888 } SPM_PERFMON_STATE; 5889 5890 /* 5891 * CP_PERFMON_STATE enum 5892 */ 5893 5894 typedef enum CP_PERFMON_STATE { 5895 CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000, 5896 CP_PERFMON_STATE_START_COUNTING = 0x00000001, 5897 CP_PERFMON_STATE_STOP_COUNTING = 0x00000002, 5898 CP_PERFMON_STATE_RESERVED_3 = 0x00000003, 5899 CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004, 5900 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005, 5901 } CP_PERFMON_STATE; 5902 5903 /* 5904 * CP_PERFMON_ENABLE_MODE enum 5905 */ 5906 5907 typedef enum CP_PERFMON_ENABLE_MODE { 5908 CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000, 5909 CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001, 5910 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002, 5911 CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003, 5912 } CP_PERFMON_ENABLE_MODE; 5913 5914 /* 5915 * CPG_PERFCOUNT_SEL enum 5916 */ 5917 5918 typedef enum CPG_PERFCOUNT_SEL { 5919 CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000, 5920 CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001, 5921 CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002, 5922 CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003, 5923 CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004, 5924 CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005, 5925 CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006, 5926 CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007, 5927 CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008, 5928 CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009, 5929 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a, 5930 CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b, 5931 CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c, 5932 CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d, 5933 CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e, 5934 CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f, 5935 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010, 5936 CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011, 5937 CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012, 5938 CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013, 5939 CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014, 5940 CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015, 5941 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016, 5942 CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017, 5943 CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018, 5944 CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019, 5945 CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a, 5946 CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b, 5947 CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c, 5948 CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d, 5949 CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e, 5950 CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f, 5951 CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020, 5952 CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021, 5953 CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x00000022, 5954 CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x00000023, 5955 CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024, 5956 CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025, 5957 CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026, 5958 CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027, 5959 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028, 5960 CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029, 5961 CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a, 5962 CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b, 5963 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c, 5964 CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d, 5965 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e, 5966 CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f, 5967 CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030, 5968 } CPG_PERFCOUNT_SEL; 5969 5970 /* 5971 * CPF_PERFCOUNT_SEL enum 5972 */ 5973 5974 typedef enum CPF_PERFCOUNT_SEL { 5975 CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000, 5976 CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001, 5977 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002, 5978 CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003, 5979 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004, 5980 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005, 5981 CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006, 5982 CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007, 5983 CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008, 5984 CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009, 5985 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a, 5986 CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b, 5987 CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c, 5988 CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d, 5989 CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e, 5990 CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0x0000000f, 5991 CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x00000010, 5992 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011, 5993 CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012, 5994 CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000013, 5995 CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000014, 5996 } CPF_PERFCOUNT_SEL; 5997 5998 /* 5999 * CPC_PERFCOUNT_SEL enum 6000 */ 6001 6002 typedef enum CPC_PERFCOUNT_SEL { 6003 CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000, 6004 CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001, 6005 CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002, 6006 CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003, 6007 CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004, 6008 CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005, 6009 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006, 6010 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007, 6011 CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008, 6012 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x00000009, 6013 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0x0000000a, 6014 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b, 6015 CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c, 6016 CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d, 6017 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e, 6018 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f, 6019 CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010, 6020 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x00000011, 6021 CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x00000012, 6022 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013, 6023 CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014, 6024 CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015, 6025 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016, 6026 CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017, 6027 CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018, 6028 } CPC_PERFCOUNT_SEL; 6029 6030 /* 6031 * CP_ALPHA_TAG_RAM_SEL enum 6032 */ 6033 6034 typedef enum CP_ALPHA_TAG_RAM_SEL { 6035 CPG_TAG_RAM = 0x00000000, 6036 CPC_TAG_RAM = 0x00000001, 6037 CPF_TAG_RAM = 0x00000002, 6038 RSV_TAG_RAM = 0x00000003, 6039 } CP_ALPHA_TAG_RAM_SEL; 6040 6041 /* 6042 * SEM_RESPONSE value 6043 */ 6044 6045 #define SEM_ECC_ERROR 0x00000000 6046 #define SEM_TRANS_ERROR 0x00000001 6047 #define SEM_FAILED 0x00000002 6048 #define SEM_PASSED 0x00000003 6049 6050 /* 6051 * IQ_RETRY_TYPE value 6052 */ 6053 6054 #define IQ_QUEUE_SLEEP 0x00000000 6055 #define IQ_OFFLOAD_RETRY 0x00000001 6056 #define IQ_SCH_WAVE_MSG 0x00000002 6057 #define IQ_SEM_REARM 0x00000003 6058 #define IQ_DEQUEUE_RETRY 0x00000004 6059 6060 /* 6061 * IQ_INTR_TYPE value 6062 */ 6063 6064 #define IQ_INTR_TYPE_PQ 0x00000000 6065 #define IQ_INTR_TYPE_IB 0x00000001 6066 #define IQ_INTR_TYPE_MQD 0x00000002 6067 6068 /* 6069 * VMID_SIZE value 6070 */ 6071 6072 #define VMID_SZ 0x00000004 6073 6074 /* 6075 * CONFIG_SPACE value 6076 */ 6077 6078 #define CONFIG_SPACE_START 0x00002000 6079 #define CONFIG_SPACE_END 0x00009fff 6080 6081 /* 6082 * CONFIG_SPACE1 value 6083 */ 6084 6085 #define CONFIG_SPACE1_START 0x00002000 6086 #define CONFIG_SPACE1_END 0x00002bff 6087 6088 /* 6089 * CONFIG_SPACE2 value 6090 */ 6091 6092 #define CONFIG_SPACE2_START 0x00003000 6093 #define CONFIG_SPACE2_END 0x00009fff 6094 6095 /* 6096 * UCONFIG_SPACE value 6097 */ 6098 6099 #define UCONFIG_SPACE_START 0x0000c000 6100 #define UCONFIG_SPACE_END 0x0000ffff 6101 6102 /* 6103 * PERSISTENT_SPACE value 6104 */ 6105 6106 #define PERSISTENT_SPACE_START 0x00002c00 6107 #define PERSISTENT_SPACE_END 0x00002fff 6108 6109 /* 6110 * CONTEXT_SPACE value 6111 */ 6112 6113 #define CONTEXT_SPACE_START 0x0000a000 6114 #define CONTEXT_SPACE_END 0x0000bfff 6115 6116 /******************************************************* 6117 * SQ_UC Enums 6118 *******************************************************/ 6119 6120 /* 6121 * VALUE_SQ_ENC_SOP1 value 6122 */ 6123 6124 #define SQ_ENC_SOP1_BITS 0xbe800000 6125 #define SQ_ENC_SOP1_MASK 0xff800000 6126 #define SQ_ENC_SOP1_FIELD 0x0000017d 6127 6128 /* 6129 * VALUE_SQ_ENC_SOPC value 6130 */ 6131 6132 #define SQ_ENC_SOPC_BITS 0xbf000000 6133 #define SQ_ENC_SOPC_MASK 0xff800000 6134 #define SQ_ENC_SOPC_FIELD 0x0000017e 6135 6136 /* 6137 * VALUE_SQ_ENC_SOPP value 6138 */ 6139 6140 #define SQ_ENC_SOPP_BITS 0xbf800000 6141 #define SQ_ENC_SOPP_MASK 0xff800000 6142 #define SQ_ENC_SOPP_FIELD 0x0000017f 6143 6144 /* 6145 * VALUE_SQ_ENC_SOPK value 6146 */ 6147 6148 #define SQ_ENC_SOPK_BITS 0xb0000000 6149 #define SQ_ENC_SOPK_MASK 0xf0000000 6150 #define SQ_ENC_SOPK_FIELD 0x0000000b 6151 6152 /* 6153 * VALUE_SQ_ENC_SOP2 value 6154 */ 6155 6156 #define SQ_ENC_SOP2_BITS 0x80000000 6157 #define SQ_ENC_SOP2_MASK 0xc0000000 6158 #define SQ_ENC_SOP2_FIELD 0x00000002 6159 6160 /* 6161 * VALUE_SQ_ENC_SMEM value 6162 */ 6163 6164 #define SQ_ENC_SMEM_BITS 0xc0000000 6165 #define SQ_ENC_SMEM_MASK 0xfc000000 6166 #define SQ_ENC_SMEM_FIELD 0x00000030 6167 6168 /* 6169 * VALUE_SQ_ENC_VOP1 value 6170 */ 6171 6172 #define SQ_ENC_VOP1_BITS 0x7e000000 6173 #define SQ_ENC_VOP1_MASK 0xfe000000 6174 #define SQ_ENC_VOP1_FIELD 0x0000003f 6175 6176 /* 6177 * VALUE_SQ_ENC_VOPC value 6178 */ 6179 6180 #define SQ_ENC_VOPC_BITS 0x7c000000 6181 #define SQ_ENC_VOPC_MASK 0xfe000000 6182 #define SQ_ENC_VOPC_FIELD 0x0000003e 6183 6184 /* 6185 * VALUE_SQ_ENC_VOP2 value 6186 */ 6187 6188 #define SQ_ENC_VOP2_BITS 0x00000000 6189 #define SQ_ENC_VOP2_MASK 0x80000000 6190 #define SQ_ENC_VOP2_FIELD 0x00000000 6191 6192 /* 6193 * VALUE_SQ_ENC_VINTRP value 6194 */ 6195 6196 #define SQ_ENC_VINTRP_BITS 0xd4000000 6197 #define SQ_ENC_VINTRP_MASK 0xfc000000 6198 #define SQ_ENC_VINTRP_FIELD 0x00000035 6199 6200 /* 6201 * VALUE_SQ_ENC_VOP3P value 6202 */ 6203 6204 #define SQ_ENC_VOP3P_BITS 0xd3800000 6205 #define SQ_ENC_VOP3P_MASK 0xff800000 6206 #define SQ_ENC_VOP3P_FIELD 0x000001a7 6207 6208 /* 6209 * VALUE_SQ_ENC_VOP3 value 6210 */ 6211 6212 #define SQ_ENC_VOP3_BITS 0xd0000000 6213 #define SQ_ENC_VOP3_MASK 0xfc000000 6214 #define SQ_ENC_VOP3_FIELD 0x00000034 6215 6216 /* 6217 * VALUE_SQ_ENC_DS value 6218 */ 6219 6220 #define SQ_ENC_DS_BITS 0xd8000000 6221 #define SQ_ENC_DS_MASK 0xfc000000 6222 #define SQ_ENC_DS_FIELD 0x00000036 6223 6224 /* 6225 * VALUE_SQ_ENC_MUBUF value 6226 */ 6227 6228 #define SQ_ENC_MUBUF_BITS 0xe0000000 6229 #define SQ_ENC_MUBUF_MASK 0xfc000000 6230 #define SQ_ENC_MUBUF_FIELD 0x00000038 6231 6232 /* 6233 * VALUE_SQ_ENC_MTBUF value 6234 */ 6235 6236 #define SQ_ENC_MTBUF_BITS 0xe8000000 6237 #define SQ_ENC_MTBUF_MASK 0xfc000000 6238 #define SQ_ENC_MTBUF_FIELD 0x0000003a 6239 6240 /* 6241 * VALUE_SQ_ENC_MIMG value 6242 */ 6243 6244 #define SQ_ENC_MIMG_BITS 0xf0000000 6245 #define SQ_ENC_MIMG_MASK 0xfc000000 6246 #define SQ_ENC_MIMG_FIELD 0x0000003c 6247 6248 /* 6249 * VALUE_SQ_ENC_EXP value 6250 */ 6251 6252 #define SQ_ENC_EXP_BITS 0xc4000000 6253 #define SQ_ENC_EXP_MASK 0xfc000000 6254 #define SQ_ENC_EXP_FIELD 0x00000031 6255 6256 /* 6257 * VALUE_SQ_ENC_FLAT value 6258 */ 6259 6260 #define SQ_ENC_FLAT_BITS 0xdc000000 6261 #define SQ_ENC_FLAT_MASK 0xfc000000 6262 #define SQ_ENC_FLAT_FIELD 0x00000037 6263 6264 /* 6265 * VALUE_SQ_HWREG_ID_SHIFT value 6266 */ 6267 6268 #define SQ_HWREG_ID_SHIFT 0x00000000 6269 6270 /* 6271 * VALUE_SQ_V_OP3P_COUNT value 6272 */ 6273 6274 #define SQ_V_OP3P_COUNT 0x00000080 6275 6276 /* 6277 * VALUE_SQ_SENDMSG_SYSTEM_SHIFT value 6278 */ 6279 6280 #define SQ_SENDMSG_SYSTEM_SHIFT 0x00000004 6281 6282 /* 6283 * VALUE_SQ_XLATE_VOP3_TO_VOP1_COUNT value 6284 */ 6285 6286 #define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x00000080 6287 6288 /* 6289 * VALUE_SQ_SRC_VGPR_BIT value 6290 */ 6291 6292 #define SQ_SRC_VGPR_BIT 0x00000100 6293 6294 /* 6295 * VALUE_SQ_V_OP1_COUNT value 6296 */ 6297 6298 #define SQ_V_OP1_COUNT 0x00000080 6299 6300 /* 6301 * VALUE_SQ_SENDMSG_STREAMID_SHIFT value 6302 */ 6303 6304 #define SQ_SENDMSG_STREAMID_SHIFT 0x00000008 6305 6306 /* 6307 * VALUE_SQ_HWREG_ID_SIZE value 6308 */ 6309 6310 #define SQ_HWREG_ID_SIZE 0x00000006 6311 6312 /* 6313 * VALUE_SQ_EXP_NUM_MRT value 6314 */ 6315 6316 #define SQ_EXP_NUM_MRT 0x00000008 6317 6318 /* 6319 * VALUE_SQ_V_OP3_3IN_OFFSET value 6320 */ 6321 6322 #define SQ_V_OP3_3IN_OFFSET 0x000001c0 6323 6324 /* 6325 * VALUE_SQ_SENDMSG_STREAMID_SIZE value 6326 */ 6327 6328 #define SQ_SENDMSG_STREAMID_SIZE 0x00000002 6329 6330 /* 6331 * VALUE_SQ_HWREG_OFFSET_SHIFT value 6332 */ 6333 6334 #define SQ_HWREG_OFFSET_SHIFT 0x00000006 6335 6336 /* 6337 * VALUE_SQ_SENDMSG_MSG_SIZE value 6338 */ 6339 6340 #define SQ_SENDMSG_MSG_SIZE 0x00000004 6341 6342 /* 6343 * VALUE_SQ_HWREG_SIZE_SHIFT value 6344 */ 6345 6346 #define SQ_HWREG_SIZE_SHIFT 0x0000000b 6347 6348 /* 6349 * VALUE_SQ_SENDMSG_SYSTEM_SIZE value 6350 */ 6351 6352 #define SQ_SENDMSG_SYSTEM_SIZE 0x00000003 6353 6354 /* 6355 * VALUE_SQ_SENDMSG_MSG_SHIFT value 6356 */ 6357 6358 #define SQ_SENDMSG_MSG_SHIFT 0x00000000 6359 6360 /* 6361 * VALUE_SQ_SENDMSG_GSOP_SIZE value 6362 */ 6363 6364 #define SQ_SENDMSG_GSOP_SIZE 0x00000002 6365 6366 /* 6367 * VALUE_SQ_SENDMSG_GSOP_SHIFT value 6368 */ 6369 6370 #define SQ_SENDMSG_GSOP_SHIFT 0x00000004 6371 6372 /* 6373 * VALUE_SQ_NUM_TTMP value 6374 */ 6375 6376 #define SQ_NUM_TTMP 0x00000010 6377 6378 /* 6379 * VALUE_SQ_XLATE_VOP3_TO_VOP3P_COUNT value 6380 */ 6381 6382 #define SQ_XLATE_VOP3_TO_VOP3P_COUNT 0x00000080 6383 6384 /* 6385 * VALUE_SQ_EXP_NUM_POS value 6386 */ 6387 6388 #define SQ_EXP_NUM_POS 0x00000004 6389 6390 /* 6391 * VALUE_SQ_XLATE_VOP3_TO_VOP3P_OFFSET value 6392 */ 6393 6394 #define SQ_XLATE_VOP3_TO_VOP3P_OFFSET 0x00000380 6395 6396 /* 6397 * VALUE_SQ_WAITCNT_EXP_SIZE value 6398 */ 6399 6400 #define SQ_WAITCNT_EXP_SIZE 0x00000003 6401 6402 /* 6403 * VALUE_SQ_V_OP2_COUNT value 6404 */ 6405 6406 #define SQ_V_OP2_COUNT 0x00000040 6407 6408 /* 6409 * VALUE_SQ_HWREG_SIZE_SIZE value 6410 */ 6411 6412 #define SQ_HWREG_SIZE_SIZE 0x00000005 6413 6414 /* 6415 * VALUE_SQ_WAITCNT_VM_SHIFT value 6416 */ 6417 6418 #define SQ_WAITCNT_VM_SHIFT 0x00000000 6419 6420 /* 6421 * VALUE_SQ_V_OP3_3IN_COUNT value 6422 */ 6423 6424 #define SQ_V_OP3_3IN_COUNT 0x000000b0 6425 6426 /* 6427 * VALUE_SQ_NUM_VGPR value 6428 */ 6429 6430 #define SQ_NUM_VGPR 0x00000100 6431 6432 /* 6433 * VALUE_SQ_EXP_NUM_PARAM value 6434 */ 6435 6436 #define SQ_EXP_NUM_PARAM 0x00000020 6437 6438 /* 6439 * VALUE_SQ_XLATE_VOP3_TO_VOPC_OFFSET value 6440 */ 6441 6442 #define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x00000000 6443 6444 /* 6445 * VALUE_SQ_V_OP3_INTRP_COUNT value 6446 */ 6447 6448 #define SQ_V_OP3_INTRP_COUNT 0x0000000c 6449 6450 /* 6451 * VALUE_SQ_WAITCNT_LGKM_SHIFT value 6452 */ 6453 6454 #define SQ_WAITCNT_LGKM_SHIFT 0x00000008 6455 6456 /* 6457 * VALUE_SQ_XLATE_VOP3_TO_VOP2_OFFSET value 6458 */ 6459 6460 #define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x00000100 6461 6462 /* 6463 * VALUE_SQ_V_OP3_2IN_OFFSET value 6464 */ 6465 6466 #define SQ_V_OP3_2IN_OFFSET 0x00000280 6467 6468 /* 6469 * VALUE_SQ_V_INTRP_COUNT value 6470 */ 6471 6472 #define SQ_V_INTRP_COUNT 0x00000004 6473 6474 /* 6475 * VALUE_SQ_XLATE_VOP3_TO_VINTRP_OFFSET value 6476 */ 6477 6478 #define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x00000270 6479 6480 /* 6481 * VALUE_SQ_WAITCNT_LGKM_SIZE value 6482 */ 6483 6484 #define SQ_WAITCNT_LGKM_SIZE 0x00000004 6485 6486 /* 6487 * VALUE_SQ_EXP_NUM_GDS value 6488 */ 6489 6490 #define SQ_EXP_NUM_GDS 0x00000005 6491 6492 /* 6493 * VALUE_SQ_HWREG_OFFSET_SIZE value 6494 */ 6495 6496 #define SQ_HWREG_OFFSET_SIZE 0x00000005 6497 6498 /* 6499 * VALUE_SQ_WAITCNT_VM_SIZE value 6500 */ 6501 6502 #define SQ_WAITCNT_VM_SIZE 0x00000004 6503 6504 /* 6505 * VALUE_SQ_V_OP3_2IN_COUNT value 6506 */ 6507 6508 #define SQ_V_OP3_2IN_COUNT 0x00000080 6509 6510 /* 6511 * VALUE_SQ_XLATE_VOP3_TO_VINTRP_COUNT value 6512 */ 6513 6514 #define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x00000004 6515 6516 /* 6517 * VALUE_SQ_XLATE_VOP3_TO_VOPC_COUNT value 6518 */ 6519 6520 #define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x00000100 6521 6522 /* 6523 * VALUE_SQ_NUM_ATTR value 6524 */ 6525 6526 #define SQ_NUM_ATTR 0x00000021 6527 6528 /* 6529 * VALUE_SQ_V_OPC_COUNT value 6530 */ 6531 6532 #define SQ_V_OPC_COUNT 0x00000100 6533 6534 /* 6535 * VALUE_SQ_V_OP3_INTRP_OFFSET value 6536 */ 6537 6538 #define SQ_V_OP3_INTRP_OFFSET 0x00000274 6539 6540 /* 6541 * VALUE_SQ_XLATE_VOP3_TO_VOP2_COUNT value 6542 */ 6543 6544 #define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x00000040 6545 6546 /* 6547 * VALUE_SQ_WAITCNT_EXP_SHIFT value 6548 */ 6549 6550 #define SQ_WAITCNT_EXP_SHIFT 0x00000004 6551 6552 /* 6553 * VALUE_SQ_XLATE_VOP3_TO_VOP1_OFFSET value 6554 */ 6555 6556 #define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x00000140 6557 6558 /* 6559 * VALUE_SQ_NUM_SGPR value 6560 */ 6561 6562 #define SQ_NUM_SGPR 0x00000066 6563 6564 /* 6565 * VALUE_SQ_FLAT_SCRATCH_LOHI value 6566 */ 6567 6568 #define SQ_FLAT_SCRATCH_LO 0x00000066 6569 #define SQ_FLAT_SCRATCH_HI 0x00000067 6570 6571 /* 6572 * VALUE_SQ_OP_VOP3 value 6573 */ 6574 6575 #define SQ_V_MAD_LEGACY_F32 0x000001c0 6576 #define SQ_V_MAD_F32 0x000001c1 6577 #define SQ_V_MAD_I32_I24 0x000001c2 6578 #define SQ_V_MAD_U32_U24 0x000001c3 6579 #define SQ_V_CUBEID_F32 0x000001c4 6580 #define SQ_V_CUBESC_F32 0x000001c5 6581 #define SQ_V_CUBETC_F32 0x000001c6 6582 #define SQ_V_CUBEMA_F32 0x000001c7 6583 #define SQ_V_BFE_U32 0x000001c8 6584 #define SQ_V_BFE_I32 0x000001c9 6585 #define SQ_V_BFI_B32 0x000001ca 6586 #define SQ_V_FMA_F32 0x000001cb 6587 #define SQ_V_FMA_F64 0x000001cc 6588 #define SQ_V_LERP_U8 0x000001cd 6589 #define SQ_V_ALIGNBIT_B32 0x000001ce 6590 #define SQ_V_ALIGNBYTE_B32 0x000001cf 6591 #define SQ_V_MIN3_F32 0x000001d0 6592 #define SQ_V_MIN3_I32 0x000001d1 6593 #define SQ_V_MIN3_U32 0x000001d2 6594 #define SQ_V_MAX3_F32 0x000001d3 6595 #define SQ_V_MAX3_I32 0x000001d4 6596 #define SQ_V_MAX3_U32 0x000001d5 6597 #define SQ_V_MED3_F32 0x000001d6 6598 #define SQ_V_MED3_I32 0x000001d7 6599 #define SQ_V_MED3_U32 0x000001d8 6600 #define SQ_V_SAD_U8 0x000001d9 6601 #define SQ_V_SAD_HI_U8 0x000001da 6602 #define SQ_V_SAD_U16 0x000001db 6603 #define SQ_V_SAD_U32 0x000001dc 6604 #define SQ_V_CVT_PK_U8_F32 0x000001dd 6605 #define SQ_V_DIV_FIXUP_F32 0x000001de 6606 #define SQ_V_DIV_FIXUP_F64 0x000001df 6607 #define SQ_V_DIV_SCALE_F32 0x000001e0 6608 #define SQ_V_DIV_SCALE_F64 0x000001e1 6609 #define SQ_V_DIV_FMAS_F32 0x000001e2 6610 #define SQ_V_DIV_FMAS_F64 0x000001e3 6611 #define SQ_V_MSAD_U8 0x000001e4 6612 #define SQ_V_QSAD_PK_U16_U8 0x000001e5 6613 #define SQ_V_MQSAD_PK_U16_U8 0x000001e6 6614 #define SQ_V_MQSAD_U32_U8 0x000001e7 6615 #define SQ_V_MAD_U64_U32 0x000001e8 6616 #define SQ_V_MAD_I64_I32 0x000001e9 6617 #define SQ_V_MAD_LEGACY_F16 0x000001ea 6618 #define SQ_V_MAD_LEGACY_U16 0x000001eb 6619 #define SQ_V_MAD_LEGACY_I16 0x000001ec 6620 #define SQ_V_PERM_B32 0x000001ed 6621 #define SQ_V_FMA_LEGACY_F16 0x000001ee 6622 #define SQ_V_DIV_FIXUP_LEGACY_F16 0x000001ef 6623 #define SQ_V_CVT_PKACCUM_U8_F32 0x000001f0 6624 #define SQ_V_MAD_U32_U16 0x000001f1 6625 #define SQ_V_MAD_I32_I16 0x000001f2 6626 #define SQ_V_XAD_U32 0x000001f3 6627 #define SQ_V_MIN3_F16 0x000001f4 6628 #define SQ_V_MIN3_I16 0x000001f5 6629 #define SQ_V_MIN3_U16 0x000001f6 6630 #define SQ_V_MAX3_F16 0x000001f7 6631 #define SQ_V_MAX3_I16 0x000001f8 6632 #define SQ_V_MAX3_U16 0x000001f9 6633 #define SQ_V_MED3_F16 0x000001fa 6634 #define SQ_V_MED3_I16 0x000001fb 6635 #define SQ_V_MED3_U16 0x000001fc 6636 #define SQ_V_LSHL_ADD_U32 0x000001fd 6637 #define SQ_V_ADD_LSHL_U32 0x000001fe 6638 #define SQ_V_ADD3_U32 0x000001ff 6639 #define SQ_V_LSHL_OR_B32 0x00000200 6640 #define SQ_V_AND_OR_B32 0x00000201 6641 #define SQ_V_OR3_B32 0x00000202 6642 #define SQ_V_MAD_F16 0x00000203 6643 #define SQ_V_MAD_U16 0x00000204 6644 #define SQ_V_MAD_I16 0x00000205 6645 #define SQ_V_FMA_F16 0x00000206 6646 #define SQ_V_DIV_FIXUP_F16 0x00000207 6647 #define SQ_V_INTERP_P1LL_F16 0x00000274 6648 #define SQ_V_INTERP_P1LV_F16 0x00000275 6649 #define SQ_V_INTERP_P2_LEGACY_F16 0x00000276 6650 #define SQ_V_INTERP_P2_F16 0x00000277 6651 #define SQ_V_ADD_F64 0x00000280 6652 #define SQ_V_MUL_F64 0x00000281 6653 #define SQ_V_MIN_F64 0x00000282 6654 #define SQ_V_MAX_F64 0x00000283 6655 #define SQ_V_LDEXP_F64 0x00000284 6656 #define SQ_V_MUL_LO_U32 0x00000285 6657 #define SQ_V_MUL_HI_U32 0x00000286 6658 #define SQ_V_MUL_HI_I32 0x00000287 6659 #define SQ_V_LDEXP_F32 0x00000288 6660 #define SQ_V_READLANE_B32 0x00000289 6661 #define SQ_V_WRITELANE_B32 0x0000028a 6662 #define SQ_V_BCNT_U32_B32 0x0000028b 6663 #define SQ_V_MBCNT_LO_U32_B32 0x0000028c 6664 #define SQ_V_MBCNT_HI_U32_B32 0x0000028d 6665 #define SQ_V_MAC_LEGACY_F32 0x0000028e 6666 #define SQ_V_LSHLREV_B64 0x0000028f 6667 #define SQ_V_LSHRREV_B64 0x00000290 6668 #define SQ_V_ASHRREV_I64 0x00000291 6669 #define SQ_V_TRIG_PREOP_F64 0x00000292 6670 #define SQ_V_BFM_B32 0x00000293 6671 #define SQ_V_CVT_PKNORM_I16_F32 0x00000294 6672 #define SQ_V_CVT_PKNORM_U16_F32 0x00000295 6673 #define SQ_V_CVT_PKRTZ_F16_F32 0x00000296 6674 #define SQ_V_CVT_PK_U16_U32 0x00000297 6675 #define SQ_V_CVT_PK_I16_I32 0x00000298 6676 #define SQ_V_CVT_PKNORM_I16_F16 0x00000299 6677 #define SQ_V_CVT_PKNORM_U16_F16 0x0000029a 6678 #define SQ_V_READLANE_REGRD_B32 0x0000029b 6679 #define SQ_V_ADD_I32 0x0000029c 6680 #define SQ_V_SUB_I32 0x0000029d 6681 #define SQ_V_ADD_I16 0x0000029e 6682 #define SQ_V_SUB_I16 0x0000029f 6683 #define SQ_V_PACK_B32_F16 0x000002a0 6684 6685 /* 6686 * VALUE_SQ_OP_VINTRP value 6687 */ 6688 6689 #define SQ_V_INTERP_P1_F32 0x00000000 6690 #define SQ_V_INTERP_P2_F32 0x00000001 6691 #define SQ_V_INTERP_MOV_F32 0x00000002 6692 6693 /* 6694 * VALUE_SQ_SSRC_SPECIAL_VCCZ value 6695 */ 6696 6697 #define SQ_SRC_VCCZ 0x000000fb 6698 6699 /* 6700 * VALUE_SQ_TGT_INTERNAL value 6701 */ 6702 6703 #define SQ_EXP_GDS0 0x00000018 6704 6705 /* 6706 * VALUE_SQ_OMOD value 6707 */ 6708 6709 #define SQ_OMOD_OFF 0x00000000 6710 #define SQ_OMOD_M2 0x00000001 6711 #define SQ_OMOD_M4 0x00000002 6712 #define SQ_OMOD_D2 0x00000003 6713 6714 /* 6715 * VALUE_SQ_ATTR value 6716 */ 6717 6718 #define SQ_ATTR0 0x00000000 6719 6720 /* 6721 * VALUE_SQ_TGT value 6722 */ 6723 6724 #define SQ_EXP_MRT0 0x00000000 6725 #define SQ_EXP_MRTZ 0x00000008 6726 #define SQ_EXP_NULL 0x00000009 6727 #define SQ_EXP_POS0 0x0000000c 6728 #define SQ_EXP_PARAM0 0x00000020 6729 6730 /* 6731 * VALUE_SQ_OPU_VOP3 value 6732 */ 6733 6734 #define SQ_V_OPC_OFFSET 0x00000000 6735 #define SQ_V_OP2_OFFSET 0x00000100 6736 #define SQ_V_OP1_OFFSET 0x00000140 6737 #define SQ_V_INTRP_OFFSET 0x00000270 6738 #define SQ_V_OP3P_OFFSET 0x00000380 6739 6740 /* 6741 * VALUE_SQ_OP_SOPK value 6742 */ 6743 6744 #define SQ_S_MOVK_I32 0x00000000 6745 #define SQ_S_CMOVK_I32 0x00000001 6746 #define SQ_S_CMPK_EQ_I32 0x00000002 6747 #define SQ_S_CMPK_LG_I32 0x00000003 6748 #define SQ_S_CMPK_GT_I32 0x00000004 6749 #define SQ_S_CMPK_GE_I32 0x00000005 6750 #define SQ_S_CMPK_LT_I32 0x00000006 6751 #define SQ_S_CMPK_LE_I32 0x00000007 6752 #define SQ_S_CMPK_EQ_U32 0x00000008 6753 #define SQ_S_CMPK_LG_U32 0x00000009 6754 #define SQ_S_CMPK_GT_U32 0x0000000a 6755 #define SQ_S_CMPK_GE_U32 0x0000000b 6756 #define SQ_S_CMPK_LT_U32 0x0000000c 6757 #define SQ_S_CMPK_LE_U32 0x0000000d 6758 #define SQ_S_ADDK_I32 0x0000000e 6759 #define SQ_S_MULK_I32 0x0000000f 6760 #define SQ_S_CBRANCH_I_FORK 0x00000010 6761 #define SQ_S_GETREG_B32 0x00000011 6762 #define SQ_S_SETREG_B32 0x00000012 6763 #define SQ_S_GETREG_REGRD_B32 0x00000013 6764 #define SQ_S_SETREG_IMM32_B32 0x00000014 6765 #define SQ_S_CALL_B64 0x00000015 6766 6767 /* 6768 * VALUE_SQ_COMPF value 6769 */ 6770 6771 #define SQ_F 0x00000000 6772 #define SQ_LT 0x00000001 6773 #define SQ_EQ 0x00000002 6774 #define SQ_LE 0x00000003 6775 #define SQ_GT 0x00000004 6776 #define SQ_LG 0x00000005 6777 #define SQ_GE 0x00000006 6778 #define SQ_O 0x00000007 6779 #define SQ_U 0x00000008 6780 #define SQ_NGE 0x00000009 6781 #define SQ_NLG 0x0000000a 6782 #define SQ_NGT 0x0000000b 6783 #define SQ_NLE 0x0000000c 6784 #define SQ_NEQ 0x0000000d 6785 #define SQ_NLT 0x0000000e 6786 #define SQ_TRU 0x0000000f 6787 6788 /* 6789 * VALUE_SQ_DPP_CTRL value 6790 */ 6791 6792 #define SQ_DPP_QUAD_PERM 0x00000000 6793 #define SQ_DPP_ROW_SL1 0x00000101 6794 #define SQ_DPP_ROW_SL2 0x00000102 6795 #define SQ_DPP_ROW_SL3 0x00000103 6796 #define SQ_DPP_ROW_SL4 0x00000104 6797 #define SQ_DPP_ROW_SL5 0x00000105 6798 #define SQ_DPP_ROW_SL6 0x00000106 6799 #define SQ_DPP_ROW_SL7 0x00000107 6800 #define SQ_DPP_ROW_SL8 0x00000108 6801 #define SQ_DPP_ROW_SL9 0x00000109 6802 #define SQ_DPP_ROW_SL10 0x0000010a 6803 #define SQ_DPP_ROW_SL11 0x0000010b 6804 #define SQ_DPP_ROW_SL12 0x0000010c 6805 #define SQ_DPP_ROW_SL13 0x0000010d 6806 #define SQ_DPP_ROW_SL14 0x0000010e 6807 #define SQ_DPP_ROW_SL15 0x0000010f 6808 #define SQ_DPP_ROW_SR1 0x00000111 6809 #define SQ_DPP_ROW_SR2 0x00000112 6810 #define SQ_DPP_ROW_SR3 0x00000113 6811 #define SQ_DPP_ROW_SR4 0x00000114 6812 #define SQ_DPP_ROW_SR5 0x00000115 6813 #define SQ_DPP_ROW_SR6 0x00000116 6814 #define SQ_DPP_ROW_SR7 0x00000117 6815 #define SQ_DPP_ROW_SR8 0x00000118 6816 #define SQ_DPP_ROW_SR9 0x00000119 6817 #define SQ_DPP_ROW_SR10 0x0000011a 6818 #define SQ_DPP_ROW_SR11 0x0000011b 6819 #define SQ_DPP_ROW_SR12 0x0000011c 6820 #define SQ_DPP_ROW_SR13 0x0000011d 6821 #define SQ_DPP_ROW_SR14 0x0000011e 6822 #define SQ_DPP_ROW_SR15 0x0000011f 6823 #define SQ_DPP_ROW_RR1 0x00000121 6824 #define SQ_DPP_ROW_RR2 0x00000122 6825 #define SQ_DPP_ROW_RR3 0x00000123 6826 #define SQ_DPP_ROW_RR4 0x00000124 6827 #define SQ_DPP_ROW_RR5 0x00000125 6828 #define SQ_DPP_ROW_RR6 0x00000126 6829 #define SQ_DPP_ROW_RR7 0x00000127 6830 #define SQ_DPP_ROW_RR8 0x00000128 6831 #define SQ_DPP_ROW_RR9 0x00000129 6832 #define SQ_DPP_ROW_RR10 0x0000012a 6833 #define SQ_DPP_ROW_RR11 0x0000012b 6834 #define SQ_DPP_ROW_RR12 0x0000012c 6835 #define SQ_DPP_ROW_RR13 0x0000012d 6836 #define SQ_DPP_ROW_RR14 0x0000012e 6837 #define SQ_DPP_ROW_RR15 0x0000012f 6838 #define SQ_DPP_WF_SL1 0x00000130 6839 #define SQ_DPP_WF_RL1 0x00000134 6840 #define SQ_DPP_WF_SR1 0x00000138 6841 #define SQ_DPP_WF_RR1 0x0000013c 6842 #define SQ_DPP_ROW_MIRROR 0x00000140 6843 #define SQ_DPP_ROW_HALF_MIRROR 0x00000141 6844 #define SQ_DPP_ROW_BCAST15 0x00000142 6845 #define SQ_DPP_ROW_BCAST31 0x00000143 6846 6847 /* 6848 * VALUE_SQ_VCC_LOHI value 6849 */ 6850 6851 #define SQ_VCC_LO 0x0000006a 6852 #define SQ_VCC_HI 0x0000006b 6853 6854 /* 6855 * VALUE_SQ_SSRC_SPECIAL_SCC value 6856 */ 6857 6858 #define SQ_SRC_SCC 0x000000fd 6859 6860 /* 6861 * VALUE_SQ_OP_SOP1 value 6862 */ 6863 6864 #define SQ_S_MOV_B32 0x00000000 6865 #define SQ_S_MOV_B64 0x00000001 6866 #define SQ_S_CMOV_B32 0x00000002 6867 #define SQ_S_CMOV_B64 0x00000003 6868 #define SQ_S_NOT_B32 0x00000004 6869 #define SQ_S_NOT_B64 0x00000005 6870 #define SQ_S_WQM_B32 0x00000006 6871 #define SQ_S_WQM_B64 0x00000007 6872 #define SQ_S_BREV_B32 0x00000008 6873 #define SQ_S_BREV_B64 0x00000009 6874 #define SQ_S_BCNT0_I32_B32 0x0000000a 6875 #define SQ_S_BCNT0_I32_B64 0x0000000b 6876 #define SQ_S_BCNT1_I32_B32 0x0000000c 6877 #define SQ_S_BCNT1_I32_B64 0x0000000d 6878 #define SQ_S_FF0_I32_B32 0x0000000e 6879 #define SQ_S_FF0_I32_B64 0x0000000f 6880 #define SQ_S_FF1_I32_B32 0x00000010 6881 #define SQ_S_FF1_I32_B64 0x00000011 6882 #define SQ_S_FLBIT_I32_B32 0x00000012 6883 #define SQ_S_FLBIT_I32_B64 0x00000013 6884 #define SQ_S_FLBIT_I32 0x00000014 6885 #define SQ_S_FLBIT_I32_I64 0x00000015 6886 #define SQ_S_SEXT_I32_I8 0x00000016 6887 #define SQ_S_SEXT_I32_I16 0x00000017 6888 #define SQ_S_BITSET0_B32 0x00000018 6889 #define SQ_S_BITSET0_B64 0x00000019 6890 #define SQ_S_BITSET1_B32 0x0000001a 6891 #define SQ_S_BITSET1_B64 0x0000001b 6892 #define SQ_S_GETPC_B64 0x0000001c 6893 #define SQ_S_SETPC_B64 0x0000001d 6894 #define SQ_S_SWAPPC_B64 0x0000001e 6895 #define SQ_S_RFE_B64 0x0000001f 6896 #define SQ_S_AND_SAVEEXEC_B64 0x00000020 6897 #define SQ_S_OR_SAVEEXEC_B64 0x00000021 6898 #define SQ_S_XOR_SAVEEXEC_B64 0x00000022 6899 #define SQ_S_ANDN2_SAVEEXEC_B64 0x00000023 6900 #define SQ_S_ORN2_SAVEEXEC_B64 0x00000024 6901 #define SQ_S_NAND_SAVEEXEC_B64 0x00000025 6902 #define SQ_S_NOR_SAVEEXEC_B64 0x00000026 6903 #define SQ_S_XNOR_SAVEEXEC_B64 0x00000027 6904 #define SQ_S_QUADMASK_B32 0x00000028 6905 #define SQ_S_QUADMASK_B64 0x00000029 6906 #define SQ_S_MOVRELS_B32 0x0000002a 6907 #define SQ_S_MOVRELS_B64 0x0000002b 6908 #define SQ_S_MOVRELD_B32 0x0000002c 6909 #define SQ_S_MOVRELD_B64 0x0000002d 6910 #define SQ_S_CBRANCH_JOIN 0x0000002e 6911 #define SQ_S_MOV_REGRD_B32 0x0000002f 6912 #define SQ_S_ABS_I32 0x00000030 6913 #define SQ_S_MOV_FED_B32 0x00000031 6914 #define SQ_S_SET_GPR_IDX_IDX 0x00000032 6915 #define SQ_S_ANDN1_SAVEEXEC_B64 0x00000033 6916 #define SQ_S_ORN1_SAVEEXEC_B64 0x00000034 6917 #define SQ_S_ANDN1_WREXEC_B64 0x00000035 6918 #define SQ_S_ANDN2_WREXEC_B64 0x00000036 6919 #define SQ_S_BITREPLICATE_B64_B32 0x00000037 6920 6921 /* 6922 * VALUE_SQ_MSG value 6923 */ 6924 6925 #define SQ_MSG_INTERRUPT 0x00000001 6926 #define SQ_MSG_GS 0x00000002 6927 #define SQ_MSG_GS_DONE 0x00000003 6928 #define SQ_MSG_SAVEWAVE 0x00000004 6929 #define SQ_MSG_STALL_WAVE_GEN 0x00000005 6930 #define SQ_MSG_HALT_WAVES 0x00000006 6931 #define SQ_MSG_ORDERED_PS_DONE 0x00000007 6932 #define SQ_MSG_EARLY_PRIM_DEALLOC 0x00000008 6933 #define SQ_MSG_GS_ALLOC_REQ 0x00000009 6934 #define SQ_MSG_SYSMSG 0x0000000f 6935 6936 /* 6937 * VALUE_SQ_OP_FLAT_GLBL value 6938 */ 6939 6940 #define SQ_GLOBAL_LOAD_UBYTE 0x00000010 6941 #define SQ_GLOBAL_LOAD_SBYTE 0x00000011 6942 #define SQ_GLOBAL_LOAD_USHORT 0x00000012 6943 #define SQ_GLOBAL_LOAD_SSHORT 0x00000013 6944 #define SQ_GLOBAL_LOAD_DWORD 0x00000014 6945 #define SQ_GLOBAL_LOAD_DWORDX2 0x00000015 6946 #define SQ_GLOBAL_LOAD_DWORDX3 0x00000016 6947 #define SQ_GLOBAL_LOAD_DWORDX4 0x00000017 6948 #define SQ_GLOBAL_STORE_BYTE 0x00000018 6949 #define SQ_GLOBAL_STORE_SHORT 0x0000001a 6950 #define SQ_GLOBAL_STORE_DWORD 0x0000001c 6951 #define SQ_GLOBAL_STORE_DWORDX2 0x0000001d 6952 #define SQ_GLOBAL_STORE_DWORDX3 0x0000001e 6953 #define SQ_GLOBAL_STORE_DWORDX4 0x0000001f 6954 #define SQ_GLOBAL_ATOMIC_SWAP 0x00000040 6955 #define SQ_GLOBAL_ATOMIC_CMPSWAP 0x00000041 6956 #define SQ_GLOBAL_ATOMIC_ADD 0x00000042 6957 #define SQ_GLOBAL_ATOMIC_SUB 0x00000043 6958 #define SQ_GLOBAL_ATOMIC_SMIN 0x00000044 6959 #define SQ_GLOBAL_ATOMIC_UMIN 0x00000045 6960 #define SQ_GLOBAL_ATOMIC_SMAX 0x00000046 6961 #define SQ_GLOBAL_ATOMIC_UMAX 0x00000047 6962 #define SQ_GLOBAL_ATOMIC_AND 0x00000048 6963 #define SQ_GLOBAL_ATOMIC_OR 0x00000049 6964 #define SQ_GLOBAL_ATOMIC_XOR 0x0000004a 6965 #define SQ_GLOBAL_ATOMIC_INC 0x0000004b 6966 #define SQ_GLOBAL_ATOMIC_DEC 0x0000004c 6967 #define SQ_GLOBAL_ATOMIC_SWAP_X2 0x00000060 6968 #define SQ_GLOBAL_ATOMIC_CMPSWAP_X2 0x00000061 6969 #define SQ_GLOBAL_ATOMIC_ADD_X2 0x00000062 6970 #define SQ_GLOBAL_ATOMIC_SUB_X2 0x00000063 6971 #define SQ_GLOBAL_ATOMIC_SMIN_X2 0x00000064 6972 #define SQ_GLOBAL_ATOMIC_UMIN_X2 0x00000065 6973 #define SQ_GLOBAL_ATOMIC_SMAX_X2 0x00000066 6974 #define SQ_GLOBAL_ATOMIC_UMAX_X2 0x00000067 6975 #define SQ_GLOBAL_ATOMIC_AND_X2 0x00000068 6976 #define SQ_GLOBAL_ATOMIC_OR_X2 0x00000069 6977 #define SQ_GLOBAL_ATOMIC_XOR_X2 0x0000006a 6978 #define SQ_GLOBAL_ATOMIC_INC_X2 0x0000006b 6979 #define SQ_GLOBAL_ATOMIC_DEC_X2 0x0000006c 6980 6981 /* 6982 * VALUE_SQ_VGPR value 6983 */ 6984 6985 #define SQ_VGPR0 0x00000000 6986 6987 /* 6988 * VALUE_SQ_HW_REG value 6989 */ 6990 6991 #define SQ_HW_REG_MODE 0x00000001 6992 #define SQ_HW_REG_STATUS 0x00000002 6993 #define SQ_HW_REG_TRAPSTS 0x00000003 6994 #define SQ_HW_REG_HW_ID 0x00000004 6995 #define SQ_HW_REG_GPR_ALLOC 0x00000005 6996 #define SQ_HW_REG_LDS_ALLOC 0x00000006 6997 #define SQ_HW_REG_IB_STS 0x00000007 6998 #define SQ_HW_REG_PC_LO 0x00000008 6999 #define SQ_HW_REG_PC_HI 0x00000009 7000 #define SQ_HW_REG_INST_DW0 0x0000000a 7001 #define SQ_HW_REG_INST_DW1 0x0000000b 7002 #define SQ_HW_REG_IB_DBG0 0x0000000c 7003 #define SQ_HW_REG_IB_DBG1 0x0000000d 7004 #define SQ_HW_REG_FLUSH_IB 0x0000000e 7005 #define SQ_HW_REG_SH_MEM_BASES 0x0000000f 7006 #define SQ_HW_REG_SQ_SHADER_TBA_LO 0x00000010 7007 #define SQ_HW_REG_SQ_SHADER_TBA_HI 0x00000011 7008 #define SQ_HW_REG_SQ_SHADER_TMA_LO 0x00000012 7009 #define SQ_HW_REG_SQ_SHADER_TMA_HI 0x00000013 7010 7011 /* 7012 * VALUE_SQ_OP_VOP1 value 7013 */ 7014 7015 #define SQ_V_NOP 0x00000000 7016 #define SQ_V_MOV_B32 0x00000001 7017 #define SQ_V_READFIRSTLANE_B32 0x00000002 7018 #define SQ_V_CVT_I32_F64 0x00000003 7019 #define SQ_V_CVT_F64_I32 0x00000004 7020 #define SQ_V_CVT_F32_I32 0x00000005 7021 #define SQ_V_CVT_F32_U32 0x00000006 7022 #define SQ_V_CVT_U32_F32 0x00000007 7023 #define SQ_V_CVT_I32_F32 0x00000008 7024 #define SQ_V_MOV_FED_B32 0x00000009 7025 #define SQ_V_CVT_F16_F32 0x0000000a 7026 #define SQ_V_CVT_F32_F16 0x0000000b 7027 #define SQ_V_CVT_RPI_I32_F32 0x0000000c 7028 #define SQ_V_CVT_FLR_I32_F32 0x0000000d 7029 #define SQ_V_CVT_OFF_F32_I4 0x0000000e 7030 #define SQ_V_CVT_F32_F64 0x0000000f 7031 #define SQ_V_CVT_F64_F32 0x00000010 7032 #define SQ_V_CVT_F32_UBYTE0 0x00000011 7033 #define SQ_V_CVT_F32_UBYTE1 0x00000012 7034 #define SQ_V_CVT_F32_UBYTE2 0x00000013 7035 #define SQ_V_CVT_F32_UBYTE3 0x00000014 7036 #define SQ_V_CVT_U32_F64 0x00000015 7037 #define SQ_V_CVT_F64_U32 0x00000016 7038 #define SQ_V_TRUNC_F64 0x00000017 7039 #define SQ_V_CEIL_F64 0x00000018 7040 #define SQ_V_RNDNE_F64 0x00000019 7041 #define SQ_V_FLOOR_F64 0x0000001a 7042 #define SQ_V_FRACT_F32 0x0000001b 7043 #define SQ_V_TRUNC_F32 0x0000001c 7044 #define SQ_V_CEIL_F32 0x0000001d 7045 #define SQ_V_RNDNE_F32 0x0000001e 7046 #define SQ_V_FLOOR_F32 0x0000001f 7047 #define SQ_V_EXP_F32 0x00000020 7048 #define SQ_V_LOG_F32 0x00000021 7049 #define SQ_V_RCP_F32 0x00000022 7050 #define SQ_V_RCP_IFLAG_F32 0x00000023 7051 #define SQ_V_RSQ_F32 0x00000024 7052 #define SQ_V_RCP_F64 0x00000025 7053 #define SQ_V_RSQ_F64 0x00000026 7054 #define SQ_V_SQRT_F32 0x00000027 7055 #define SQ_V_SQRT_F64 0x00000028 7056 #define SQ_V_SIN_F32 0x00000029 7057 #define SQ_V_COS_F32 0x0000002a 7058 #define SQ_V_NOT_B32 0x0000002b 7059 #define SQ_V_BFREV_B32 0x0000002c 7060 #define SQ_V_FFBH_U32 0x0000002d 7061 #define SQ_V_FFBL_B32 0x0000002e 7062 #define SQ_V_FFBH_I32 0x0000002f 7063 #define SQ_V_FREXP_EXP_I32_F64 0x00000030 7064 #define SQ_V_FREXP_MANT_F64 0x00000031 7065 #define SQ_V_FRACT_F64 0x00000032 7066 #define SQ_V_FREXP_EXP_I32_F32 0x00000033 7067 #define SQ_V_FREXP_MANT_F32 0x00000034 7068 #define SQ_V_CLREXCP 0x00000035 7069 #define SQ_V_MOV_PRSV_B32 0x00000036 7070 #define SQ_V_CVT_F16_U16 0x00000039 7071 #define SQ_V_CVT_F16_I16 0x0000003a 7072 #define SQ_V_CVT_U16_F16 0x0000003b 7073 #define SQ_V_CVT_I16_F16 0x0000003c 7074 #define SQ_V_RCP_F16 0x0000003d 7075 #define SQ_V_SQRT_F16 0x0000003e 7076 #define SQ_V_RSQ_F16 0x0000003f 7077 #define SQ_V_LOG_F16 0x00000040 7078 #define SQ_V_EXP_F16 0x00000041 7079 #define SQ_V_FREXP_MANT_F16 0x00000042 7080 #define SQ_V_FREXP_EXP_I16_F16 0x00000043 7081 #define SQ_V_FLOOR_F16 0x00000044 7082 #define SQ_V_CEIL_F16 0x00000045 7083 #define SQ_V_TRUNC_F16 0x00000046 7084 #define SQ_V_RNDNE_F16 0x00000047 7085 #define SQ_V_FRACT_F16 0x00000048 7086 #define SQ_V_SIN_F16 0x00000049 7087 #define SQ_V_COS_F16 0x0000004a 7088 #define SQ_V_EXP_LEGACY_F32 0x0000004b 7089 #define SQ_V_LOG_LEGACY_F32 0x0000004c 7090 #define SQ_V_CVT_NORM_I16_F16 0x0000004d 7091 #define SQ_V_CVT_NORM_U16_F16 0x0000004e 7092 #define SQ_V_SAT_PK_U8_I16 0x0000004f 7093 #define SQ_V_WRITELANE_IMM32 0x00000050 7094 #define SQ_V_SWAP_B32 0x00000051 7095 7096 /* 7097 * VALUE_SQ_OP_MUBUF value 7098 */ 7099 7100 #define SQ_BUFFER_LOAD_FORMAT_X 0x00000000 7101 #define SQ_BUFFER_LOAD_FORMAT_XY 0x00000001 7102 #define SQ_BUFFER_LOAD_FORMAT_XYZ 0x00000002 7103 #define SQ_BUFFER_LOAD_FORMAT_XYZW 0x00000003 7104 #define SQ_BUFFER_STORE_FORMAT_X 0x00000004 7105 #define SQ_BUFFER_STORE_FORMAT_XY 0x00000005 7106 #define SQ_BUFFER_STORE_FORMAT_XYZ 0x00000006 7107 #define SQ_BUFFER_STORE_FORMAT_XYZW 0x00000007 7108 #define SQ_BUFFER_LOAD_FORMAT_D16_X 0x00000008 7109 #define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x00000009 7110 #define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a 7111 #define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b 7112 #define SQ_BUFFER_STORE_FORMAT_D16_X 0x0000000c 7113 #define SQ_BUFFER_STORE_FORMAT_D16_XY 0x0000000d 7114 #define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0x0000000e 7115 #define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0x0000000f 7116 #define SQ_BUFFER_LOAD_UBYTE 0x00000010 7117 #define SQ_BUFFER_LOAD_SBYTE 0x00000011 7118 #define SQ_BUFFER_LOAD_USHORT 0x00000012 7119 #define SQ_BUFFER_LOAD_SSHORT 0x00000013 7120 #define SQ_BUFFER_LOAD_DWORD 0x00000014 7121 #define SQ_BUFFER_LOAD_DWORDX2 0x00000015 7122 #define SQ_BUFFER_LOAD_DWORDX3 0x00000016 7123 #define SQ_BUFFER_LOAD_DWORDX4 0x00000017 7124 #define SQ_BUFFER_STORE_BYTE 0x00000018 7125 #define SQ_BUFFER_STORE_SHORT 0x0000001a 7126 #define SQ_BUFFER_STORE_DWORD 0x0000001c 7127 #define SQ_BUFFER_STORE_DWORDX2 0x0000001d 7128 #define SQ_BUFFER_STORE_DWORDX3 0x0000001e 7129 #define SQ_BUFFER_STORE_DWORDX4 0x0000001f 7130 #define SQ_BUFFER_STORE_LDS_DWORD 0x0000003d 7131 #define SQ_BUFFER_WBINVL1 0x0000003e 7132 #define SQ_BUFFER_WBINVL1_VOL 0x0000003f 7133 #define SQ_BUFFER_ATOMIC_SWAP 0x00000040 7134 #define SQ_BUFFER_ATOMIC_CMPSWAP 0x00000041 7135 #define SQ_BUFFER_ATOMIC_ADD 0x00000042 7136 #define SQ_BUFFER_ATOMIC_SUB 0x00000043 7137 #define SQ_BUFFER_ATOMIC_SMIN 0x00000044 7138 #define SQ_BUFFER_ATOMIC_UMIN 0x00000045 7139 #define SQ_BUFFER_ATOMIC_SMAX 0x00000046 7140 #define SQ_BUFFER_ATOMIC_UMAX 0x00000047 7141 #define SQ_BUFFER_ATOMIC_AND 0x00000048 7142 #define SQ_BUFFER_ATOMIC_OR 0x00000049 7143 #define SQ_BUFFER_ATOMIC_XOR 0x0000004a 7144 #define SQ_BUFFER_ATOMIC_INC 0x0000004b 7145 #define SQ_BUFFER_ATOMIC_DEC 0x0000004c 7146 #define SQ_BUFFER_ATOMIC_SWAP_X2 0x00000060 7147 #define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061 7148 #define SQ_BUFFER_ATOMIC_ADD_X2 0x00000062 7149 #define SQ_BUFFER_ATOMIC_SUB_X2 0x00000063 7150 #define SQ_BUFFER_ATOMIC_SMIN_X2 0x00000064 7151 #define SQ_BUFFER_ATOMIC_UMIN_X2 0x00000065 7152 #define SQ_BUFFER_ATOMIC_SMAX_X2 0x00000066 7153 #define SQ_BUFFER_ATOMIC_UMAX_X2 0x00000067 7154 #define SQ_BUFFER_ATOMIC_AND_X2 0x00000068 7155 #define SQ_BUFFER_ATOMIC_OR_X2 0x00000069 7156 #define SQ_BUFFER_ATOMIC_XOR_X2 0x0000006a 7157 #define SQ_BUFFER_ATOMIC_INC_X2 0x0000006b 7158 #define SQ_BUFFER_ATOMIC_DEC_X2 0x0000006c 7159 7160 /* 7161 * VALUE_SQ_TRAP value 7162 */ 7163 7164 #define SQ_TTMP0 0x0000006c 7165 #define SQ_TTMP1 0x0000006d 7166 #define SQ_TTMP2 0x0000006e 7167 #define SQ_TTMP3 0x0000006f 7168 #define SQ_TTMP4 0x00000070 7169 #define SQ_TTMP5 0x00000071 7170 #define SQ_TTMP6 0x00000072 7171 #define SQ_TTMP7 0x00000073 7172 #define SQ_TTMP8 0x00000074 7173 #define SQ_TTMP9 0x00000075 7174 #define SQ_TTMP10 0x00000076 7175 #define SQ_TTMP11 0x00000077 7176 #define SQ_TTMP12 0x00000078 7177 #define SQ_TTMP13 0x00000079 7178 #define SQ_TTMP14 0x0000007a 7179 #define SQ_TTMP15 0x0000007b 7180 7181 /* 7182 * VALUE_SQ_OP_VOPC value 7183 */ 7184 7185 #define SQ_V_CMP_CLASS_F32 0x00000010 7186 #define SQ_V_CMPX_CLASS_F32 0x00000011 7187 #define SQ_V_CMP_CLASS_F64 0x00000012 7188 #define SQ_V_CMPX_CLASS_F64 0x00000013 7189 #define SQ_V_CMP_CLASS_F16 0x00000014 7190 #define SQ_V_CMPX_CLASS_F16 0x00000015 7191 #define SQ_V_CMP_F_F16 0x00000020 7192 #define SQ_V_CMP_LT_F16 0x00000021 7193 #define SQ_V_CMP_EQ_F16 0x00000022 7194 #define SQ_V_CMP_LE_F16 0x00000023 7195 #define SQ_V_CMP_GT_F16 0x00000024 7196 #define SQ_V_CMP_LG_F16 0x00000025 7197 #define SQ_V_CMP_GE_F16 0x00000026 7198 #define SQ_V_CMP_O_F16 0x00000027 7199 #define SQ_V_CMP_U_F16 0x00000028 7200 #define SQ_V_CMP_NGE_F16 0x00000029 7201 #define SQ_V_CMP_NLG_F16 0x0000002a 7202 #define SQ_V_CMP_NGT_F16 0x0000002b 7203 #define SQ_V_CMP_NLE_F16 0x0000002c 7204 #define SQ_V_CMP_NEQ_F16 0x0000002d 7205 #define SQ_V_CMP_NLT_F16 0x0000002e 7206 #define SQ_V_CMP_TRU_F16 0x0000002f 7207 #define SQ_V_CMPX_F_F16 0x00000030 7208 #define SQ_V_CMPX_LT_F16 0x00000031 7209 #define SQ_V_CMPX_EQ_F16 0x00000032 7210 #define SQ_V_CMPX_LE_F16 0x00000033 7211 #define SQ_V_CMPX_GT_F16 0x00000034 7212 #define SQ_V_CMPX_LG_F16 0x00000035 7213 #define SQ_V_CMPX_GE_F16 0x00000036 7214 #define SQ_V_CMPX_O_F16 0x00000037 7215 #define SQ_V_CMPX_U_F16 0x00000038 7216 #define SQ_V_CMPX_NGE_F16 0x00000039 7217 #define SQ_V_CMPX_NLG_F16 0x0000003a 7218 #define SQ_V_CMPX_NGT_F16 0x0000003b 7219 #define SQ_V_CMPX_NLE_F16 0x0000003c 7220 #define SQ_V_CMPX_NEQ_F16 0x0000003d 7221 #define SQ_V_CMPX_NLT_F16 0x0000003e 7222 #define SQ_V_CMPX_TRU_F16 0x0000003f 7223 #define SQ_V_CMP_F_F32 0x00000040 7224 #define SQ_V_CMP_LT_F32 0x00000041 7225 #define SQ_V_CMP_EQ_F32 0x00000042 7226 #define SQ_V_CMP_LE_F32 0x00000043 7227 #define SQ_V_CMP_GT_F32 0x00000044 7228 #define SQ_V_CMP_LG_F32 0x00000045 7229 #define SQ_V_CMP_GE_F32 0x00000046 7230 #define SQ_V_CMP_O_F32 0x00000047 7231 #define SQ_V_CMP_U_F32 0x00000048 7232 #define SQ_V_CMP_NGE_F32 0x00000049 7233 #define SQ_V_CMP_NLG_F32 0x0000004a 7234 #define SQ_V_CMP_NGT_F32 0x0000004b 7235 #define SQ_V_CMP_NLE_F32 0x0000004c 7236 #define SQ_V_CMP_NEQ_F32 0x0000004d 7237 #define SQ_V_CMP_NLT_F32 0x0000004e 7238 #define SQ_V_CMP_TRU_F32 0x0000004f 7239 #define SQ_V_CMPX_F_F32 0x00000050 7240 #define SQ_V_CMPX_LT_F32 0x00000051 7241 #define SQ_V_CMPX_EQ_F32 0x00000052 7242 #define SQ_V_CMPX_LE_F32 0x00000053 7243 #define SQ_V_CMPX_GT_F32 0x00000054 7244 #define SQ_V_CMPX_LG_F32 0x00000055 7245 #define SQ_V_CMPX_GE_F32 0x00000056 7246 #define SQ_V_CMPX_O_F32 0x00000057 7247 #define SQ_V_CMPX_U_F32 0x00000058 7248 #define SQ_V_CMPX_NGE_F32 0x00000059 7249 #define SQ_V_CMPX_NLG_F32 0x0000005a 7250 #define SQ_V_CMPX_NGT_F32 0x0000005b 7251 #define SQ_V_CMPX_NLE_F32 0x0000005c 7252 #define SQ_V_CMPX_NEQ_F32 0x0000005d 7253 #define SQ_V_CMPX_NLT_F32 0x0000005e 7254 #define SQ_V_CMPX_TRU_F32 0x0000005f 7255 #define SQ_V_CMP_F_F64 0x00000060 7256 #define SQ_V_CMP_LT_F64 0x00000061 7257 #define SQ_V_CMP_EQ_F64 0x00000062 7258 #define SQ_V_CMP_LE_F64 0x00000063 7259 #define SQ_V_CMP_GT_F64 0x00000064 7260 #define SQ_V_CMP_LG_F64 0x00000065 7261 #define SQ_V_CMP_GE_F64 0x00000066 7262 #define SQ_V_CMP_O_F64 0x00000067 7263 #define SQ_V_CMP_U_F64 0x00000068 7264 #define SQ_V_CMP_NGE_F64 0x00000069 7265 #define SQ_V_CMP_NLG_F64 0x0000006a 7266 #define SQ_V_CMP_NGT_F64 0x0000006b 7267 #define SQ_V_CMP_NLE_F64 0x0000006c 7268 #define SQ_V_CMP_NEQ_F64 0x0000006d 7269 #define SQ_V_CMP_NLT_F64 0x0000006e 7270 #define SQ_V_CMP_TRU_F64 0x0000006f 7271 #define SQ_V_CMPX_F_F64 0x00000070 7272 #define SQ_V_CMPX_LT_F64 0x00000071 7273 #define SQ_V_CMPX_EQ_F64 0x00000072 7274 #define SQ_V_CMPX_LE_F64 0x00000073 7275 #define SQ_V_CMPX_GT_F64 0x00000074 7276 #define SQ_V_CMPX_LG_F64 0x00000075 7277 #define SQ_V_CMPX_GE_F64 0x00000076 7278 #define SQ_V_CMPX_O_F64 0x00000077 7279 #define SQ_V_CMPX_U_F64 0x00000078 7280 #define SQ_V_CMPX_NGE_F64 0x00000079 7281 #define SQ_V_CMPX_NLG_F64 0x0000007a 7282 #define SQ_V_CMPX_NGT_F64 0x0000007b 7283 #define SQ_V_CMPX_NLE_F64 0x0000007c 7284 #define SQ_V_CMPX_NEQ_F64 0x0000007d 7285 #define SQ_V_CMPX_NLT_F64 0x0000007e 7286 #define SQ_V_CMPX_TRU_F64 0x0000007f 7287 #define SQ_V_CMP_F_I16 0x000000a0 7288 #define SQ_V_CMP_LT_I16 0x000000a1 7289 #define SQ_V_CMP_EQ_I16 0x000000a2 7290 #define SQ_V_CMP_LE_I16 0x000000a3 7291 #define SQ_V_CMP_GT_I16 0x000000a4 7292 #define SQ_V_CMP_NE_I16 0x000000a5 7293 #define SQ_V_CMP_GE_I16 0x000000a6 7294 #define SQ_V_CMP_T_I16 0x000000a7 7295 #define SQ_V_CMP_F_U16 0x000000a8 7296 #define SQ_V_CMP_LT_U16 0x000000a9 7297 #define SQ_V_CMP_EQ_U16 0x000000aa 7298 #define SQ_V_CMP_LE_U16 0x000000ab 7299 #define SQ_V_CMP_GT_U16 0x000000ac 7300 #define SQ_V_CMP_NE_U16 0x000000ad 7301 #define SQ_V_CMP_GE_U16 0x000000ae 7302 #define SQ_V_CMP_T_U16 0x000000af 7303 #define SQ_V_CMPX_F_I16 0x000000b0 7304 #define SQ_V_CMPX_LT_I16 0x000000b1 7305 #define SQ_V_CMPX_EQ_I16 0x000000b2 7306 #define SQ_V_CMPX_LE_I16 0x000000b3 7307 #define SQ_V_CMPX_GT_I16 0x000000b4 7308 #define SQ_V_CMPX_NE_I16 0x000000b5 7309 #define SQ_V_CMPX_GE_I16 0x000000b6 7310 #define SQ_V_CMPX_T_I16 0x000000b7 7311 #define SQ_V_CMPX_F_U16 0x000000b8 7312 #define SQ_V_CMPX_LT_U16 0x000000b9 7313 #define SQ_V_CMPX_EQ_U16 0x000000ba 7314 #define SQ_V_CMPX_LE_U16 0x000000bb 7315 #define SQ_V_CMPX_GT_U16 0x000000bc 7316 #define SQ_V_CMPX_NE_U16 0x000000bd 7317 #define SQ_V_CMPX_GE_U16 0x000000be 7318 #define SQ_V_CMPX_T_U16 0x000000bf 7319 #define SQ_V_CMP_F_I32 0x000000c0 7320 #define SQ_V_CMP_LT_I32 0x000000c1 7321 #define SQ_V_CMP_EQ_I32 0x000000c2 7322 #define SQ_V_CMP_LE_I32 0x000000c3 7323 #define SQ_V_CMP_GT_I32 0x000000c4 7324 #define SQ_V_CMP_NE_I32 0x000000c5 7325 #define SQ_V_CMP_GE_I32 0x000000c6 7326 #define SQ_V_CMP_T_I32 0x000000c7 7327 #define SQ_V_CMP_F_U32 0x000000c8 7328 #define SQ_V_CMP_LT_U32 0x000000c9 7329 #define SQ_V_CMP_EQ_U32 0x000000ca 7330 #define SQ_V_CMP_LE_U32 0x000000cb 7331 #define SQ_V_CMP_GT_U32 0x000000cc 7332 #define SQ_V_CMP_NE_U32 0x000000cd 7333 #define SQ_V_CMP_GE_U32 0x000000ce 7334 #define SQ_V_CMP_T_U32 0x000000cf 7335 #define SQ_V_CMPX_F_I32 0x000000d0 7336 #define SQ_V_CMPX_LT_I32 0x000000d1 7337 #define SQ_V_CMPX_EQ_I32 0x000000d2 7338 #define SQ_V_CMPX_LE_I32 0x000000d3 7339 #define SQ_V_CMPX_GT_I32 0x000000d4 7340 #define SQ_V_CMPX_NE_I32 0x000000d5 7341 #define SQ_V_CMPX_GE_I32 0x000000d6 7342 #define SQ_V_CMPX_T_I32 0x000000d7 7343 #define SQ_V_CMPX_F_U32 0x000000d8 7344 #define SQ_V_CMPX_LT_U32 0x000000d9 7345 #define SQ_V_CMPX_EQ_U32 0x000000da 7346 #define SQ_V_CMPX_LE_U32 0x000000db 7347 #define SQ_V_CMPX_GT_U32 0x000000dc 7348 #define SQ_V_CMPX_NE_U32 0x000000dd 7349 #define SQ_V_CMPX_GE_U32 0x000000de 7350 #define SQ_V_CMPX_T_U32 0x000000df 7351 #define SQ_V_CMP_F_I64 0x000000e0 7352 #define SQ_V_CMP_LT_I64 0x000000e1 7353 #define SQ_V_CMP_EQ_I64 0x000000e2 7354 #define SQ_V_CMP_LE_I64 0x000000e3 7355 #define SQ_V_CMP_GT_I64 0x000000e4 7356 #define SQ_V_CMP_NE_I64 0x000000e5 7357 #define SQ_V_CMP_GE_I64 0x000000e6 7358 #define SQ_V_CMP_T_I64 0x000000e7 7359 #define SQ_V_CMP_F_U64 0x000000e8 7360 #define SQ_V_CMP_LT_U64 0x000000e9 7361 #define SQ_V_CMP_EQ_U64 0x000000ea 7362 #define SQ_V_CMP_LE_U64 0x000000eb 7363 #define SQ_V_CMP_GT_U64 0x000000ec 7364 #define SQ_V_CMP_NE_U64 0x000000ed 7365 #define SQ_V_CMP_GE_U64 0x000000ee 7366 #define SQ_V_CMP_T_U64 0x000000ef 7367 #define SQ_V_CMPX_F_I64 0x000000f0 7368 #define SQ_V_CMPX_LT_I64 0x000000f1 7369 #define SQ_V_CMPX_EQ_I64 0x000000f2 7370 #define SQ_V_CMPX_LE_I64 0x000000f3 7371 #define SQ_V_CMPX_GT_I64 0x000000f4 7372 #define SQ_V_CMPX_NE_I64 0x000000f5 7373 #define SQ_V_CMPX_GE_I64 0x000000f6 7374 #define SQ_V_CMPX_T_I64 0x000000f7 7375 #define SQ_V_CMPX_F_U64 0x000000f8 7376 #define SQ_V_CMPX_LT_U64 0x000000f9 7377 #define SQ_V_CMPX_EQ_U64 0x000000fa 7378 #define SQ_V_CMPX_LE_U64 0x000000fb 7379 #define SQ_V_CMPX_GT_U64 0x000000fc 7380 #define SQ_V_CMPX_NE_U64 0x000000fd 7381 #define SQ_V_CMPX_GE_U64 0x000000fe 7382 #define SQ_V_CMPX_T_U64 0x000000ff 7383 7384 /* 7385 * VALUE_SQ_DPP_CTRL_R_1_15 value 7386 */ 7387 7388 #define SQ_R1 0x00000001 7389 #define SQ_R2 0x00000002 7390 #define SQ_R3 0x00000003 7391 #define SQ_R4 0x00000004 7392 #define SQ_R5 0x00000005 7393 #define SQ_R6 0x00000006 7394 #define SQ_R7 0x00000007 7395 #define SQ_R8 0x00000008 7396 #define SQ_R9 0x00000009 7397 #define SQ_R10 0x0000000a 7398 #define SQ_R11 0x0000000b 7399 #define SQ_R12 0x0000000c 7400 #define SQ_R13 0x0000000d 7401 #define SQ_R14 0x0000000e 7402 #define SQ_R15 0x0000000f 7403 7404 /* 7405 * VALUE_SQ_SSRC_SPECIAL_LDS value 7406 */ 7407 7408 #define SQ_SRC_LDS_DIRECT 0x000000fe 7409 7410 /* 7411 * VALUE_SQ_OP_EXP value 7412 */ 7413 7414 #define SQ_EXP 0x00000000 7415 7416 /* 7417 * VALUE_SQ_SDST_M0 value 7418 */ 7419 7420 #define SQ_M0 0x0000007c 7421 7422 /* 7423 * VALUE_SQ_OP_MIMG value 7424 */ 7425 7426 #define SQ_IMAGE_LOAD 0x00000000 7427 #define SQ_IMAGE_LOAD_MIP 0x00000001 7428 #define SQ_IMAGE_LOAD_PCK 0x00000002 7429 #define SQ_IMAGE_LOAD_PCK_SGN 0x00000003 7430 #define SQ_IMAGE_LOAD_MIP_PCK 0x00000004 7431 #define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x00000005 7432 #define SQ_IMAGE_STORE 0x00000008 7433 #define SQ_IMAGE_STORE_MIP 0x00000009 7434 #define SQ_IMAGE_STORE_PCK 0x0000000a 7435 #define SQ_IMAGE_STORE_MIP_PCK 0x0000000b 7436 #define SQ_IMAGE_GET_RESINFO 0x0000000e 7437 #define SQ_IMAGE_ATOMIC_SWAP 0x00000010 7438 #define SQ_IMAGE_ATOMIC_CMPSWAP 0x00000011 7439 #define SQ_IMAGE_ATOMIC_ADD 0x00000012 7440 #define SQ_IMAGE_ATOMIC_SUB 0x00000013 7441 #define SQ_IMAGE_ATOMIC_SMIN 0x00000014 7442 #define SQ_IMAGE_ATOMIC_UMIN 0x00000015 7443 #define SQ_IMAGE_ATOMIC_SMAX 0x00000016 7444 #define SQ_IMAGE_ATOMIC_UMAX 0x00000017 7445 #define SQ_IMAGE_ATOMIC_AND 0x00000018 7446 #define SQ_IMAGE_ATOMIC_OR 0x00000019 7447 #define SQ_IMAGE_ATOMIC_XOR 0x0000001a 7448 #define SQ_IMAGE_ATOMIC_INC 0x0000001b 7449 #define SQ_IMAGE_ATOMIC_DEC 0x0000001c 7450 #define SQ_IMAGE_SAMPLE 0x00000020 7451 #define SQ_IMAGE_SAMPLE_CL 0x00000021 7452 #define SQ_IMAGE_SAMPLE_D 0x00000022 7453 #define SQ_IMAGE_SAMPLE_D_CL 0x00000023 7454 #define SQ_IMAGE_SAMPLE_L 0x00000024 7455 #define SQ_IMAGE_SAMPLE_B 0x00000025 7456 #define SQ_IMAGE_SAMPLE_B_CL 0x00000026 7457 #define SQ_IMAGE_SAMPLE_LZ 0x00000027 7458 #define SQ_IMAGE_SAMPLE_C 0x00000028 7459 #define SQ_IMAGE_SAMPLE_C_CL 0x00000029 7460 #define SQ_IMAGE_SAMPLE_C_D 0x0000002a 7461 #define SQ_IMAGE_SAMPLE_C_D_CL 0x0000002b 7462 #define SQ_IMAGE_SAMPLE_C_L 0x0000002c 7463 #define SQ_IMAGE_SAMPLE_C_B 0x0000002d 7464 #define SQ_IMAGE_SAMPLE_C_B_CL 0x0000002e 7465 #define SQ_IMAGE_SAMPLE_C_LZ 0x0000002f 7466 #define SQ_IMAGE_SAMPLE_O 0x00000030 7467 #define SQ_IMAGE_SAMPLE_CL_O 0x00000031 7468 #define SQ_IMAGE_SAMPLE_D_O 0x00000032 7469 #define SQ_IMAGE_SAMPLE_D_CL_O 0x00000033 7470 #define SQ_IMAGE_SAMPLE_L_O 0x00000034 7471 #define SQ_IMAGE_SAMPLE_B_O 0x00000035 7472 #define SQ_IMAGE_SAMPLE_B_CL_O 0x00000036 7473 #define SQ_IMAGE_SAMPLE_LZ_O 0x00000037 7474 #define SQ_IMAGE_SAMPLE_C_O 0x00000038 7475 #define SQ_IMAGE_SAMPLE_C_CL_O 0x00000039 7476 #define SQ_IMAGE_SAMPLE_C_D_O 0x0000003a 7477 #define SQ_IMAGE_SAMPLE_C_D_CL_O 0x0000003b 7478 #define SQ_IMAGE_SAMPLE_C_L_O 0x0000003c 7479 #define SQ_IMAGE_SAMPLE_C_B_O 0x0000003d 7480 #define SQ_IMAGE_SAMPLE_C_B_CL_O 0x0000003e 7481 #define SQ_IMAGE_SAMPLE_C_LZ_O 0x0000003f 7482 #define SQ_IMAGE_GATHER4 0x00000040 7483 #define SQ_IMAGE_GATHER4_CL 0x00000041 7484 #define SQ_IMAGE_GATHER4H 0x00000042 7485 #define SQ_IMAGE_GATHER4_L 0x00000044 7486 #define SQ_IMAGE_GATHER4_B 0x00000045 7487 #define SQ_IMAGE_GATHER4_B_CL 0x00000046 7488 #define SQ_IMAGE_GATHER4_LZ 0x00000047 7489 #define SQ_IMAGE_GATHER4_C 0x00000048 7490 #define SQ_IMAGE_GATHER4_C_CL 0x00000049 7491 #define SQ_IMAGE_GATHER4H_PCK 0x0000004a 7492 #define SQ_IMAGE_GATHER8H_PCK 0x0000004b 7493 #define SQ_IMAGE_GATHER4_C_L 0x0000004c 7494 #define SQ_IMAGE_GATHER4_C_B 0x0000004d 7495 #define SQ_IMAGE_GATHER4_C_B_CL 0x0000004e 7496 #define SQ_IMAGE_GATHER4_C_LZ 0x0000004f 7497 #define SQ_IMAGE_GATHER4_O 0x00000050 7498 #define SQ_IMAGE_GATHER4_CL_O 0x00000051 7499 #define SQ_IMAGE_GATHER4_L_O 0x00000054 7500 #define SQ_IMAGE_GATHER4_B_O 0x00000055 7501 #define SQ_IMAGE_GATHER4_B_CL_O 0x00000056 7502 #define SQ_IMAGE_GATHER4_LZ_O 0x00000057 7503 #define SQ_IMAGE_GATHER4_C_O 0x00000058 7504 #define SQ_IMAGE_GATHER4_C_CL_O 0x00000059 7505 #define SQ_IMAGE_GATHER4_C_L_O 0x0000005c 7506 #define SQ_IMAGE_GATHER4_C_B_O 0x0000005d 7507 #define SQ_IMAGE_GATHER4_C_B_CL_O 0x0000005e 7508 #define SQ_IMAGE_GATHER4_C_LZ_O 0x0000005f 7509 #define SQ_IMAGE_GET_LOD 0x00000060 7510 #define SQ_IMAGE_SAMPLE_CD 0x00000068 7511 #define SQ_IMAGE_SAMPLE_CD_CL 0x00000069 7512 #define SQ_IMAGE_SAMPLE_C_CD 0x0000006a 7513 #define SQ_IMAGE_SAMPLE_C_CD_CL 0x0000006b 7514 #define SQ_IMAGE_SAMPLE_CD_O 0x0000006c 7515 #define SQ_IMAGE_SAMPLE_CD_CL_O 0x0000006d 7516 #define SQ_IMAGE_SAMPLE_C_CD_O 0x0000006e 7517 #define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x0000006f 7518 #define SQ_IMAGE_RSRC256 0x0000007e 7519 #define SQ_IMAGE_SAMPLER 0x0000007f 7520 7521 /* 7522 * VALUE_SQ_SSRC_SPECIAL_NOLIT value 7523 */ 7524 7525 #define SQ_SRC_64_INT 0x000000c0 7526 #define SQ_SRC_M_1_INT 0x000000c1 7527 #define SQ_SRC_M_2_INT 0x000000c2 7528 #define SQ_SRC_M_3_INT 0x000000c3 7529 #define SQ_SRC_M_4_INT 0x000000c4 7530 #define SQ_SRC_M_5_INT 0x000000c5 7531 #define SQ_SRC_M_6_INT 0x000000c6 7532 #define SQ_SRC_M_7_INT 0x000000c7 7533 #define SQ_SRC_M_8_INT 0x000000c8 7534 #define SQ_SRC_M_9_INT 0x000000c9 7535 #define SQ_SRC_M_10_INT 0x000000ca 7536 #define SQ_SRC_M_11_INT 0x000000cb 7537 #define SQ_SRC_M_12_INT 0x000000cc 7538 #define SQ_SRC_M_13_INT 0x000000cd 7539 #define SQ_SRC_M_14_INT 0x000000ce 7540 #define SQ_SRC_M_15_INT 0x000000cf 7541 #define SQ_SRC_M_16_INT 0x000000d0 7542 #define SQ_SRC_0_5 0x000000f0 7543 #define SQ_SRC_M_0_5 0x000000f1 7544 #define SQ_SRC_1 0x000000f2 7545 #define SQ_SRC_M_1 0x000000f3 7546 #define SQ_SRC_2 0x000000f4 7547 #define SQ_SRC_M_2 0x000000f5 7548 #define SQ_SRC_4 0x000000f6 7549 #define SQ_SRC_M_4 0x000000f7 7550 #define SQ_SRC_INV_2PI 0x000000f8 7551 7552 /* 7553 * VALUE_SQ_SSRC_SPECIAL_DPP value 7554 */ 7555 7556 #define SQ_SRC_DPP 0x000000fa 7557 7558 /* 7559 * VALUE_SQ_SSRC_SPECIAL_APERTURE value 7560 */ 7561 7562 #define SQ_SRC_SHARED_BASE 0x000000eb 7563 #define SQ_SRC_SHARED_LIMIT 0x000000ec 7564 #define SQ_SRC_PRIVATE_BASE 0x000000ed 7565 #define SQ_SRC_PRIVATE_LIMIT 0x000000ee 7566 7567 /* 7568 * VALUE_SQ_DPP_CTRL_L_1_15 value 7569 */ 7570 7571 #define SQ_L1 0x00000001 7572 #define SQ_L2 0x00000002 7573 #define SQ_L3 0x00000003 7574 #define SQ_L4 0x00000004 7575 #define SQ_L5 0x00000005 7576 #define SQ_L6 0x00000006 7577 #define SQ_L7 0x00000007 7578 #define SQ_L8 0x00000008 7579 #define SQ_L9 0x00000009 7580 #define SQ_L10 0x0000000a 7581 #define SQ_L11 0x0000000b 7582 #define SQ_L12 0x0000000c 7583 #define SQ_L13 0x0000000d 7584 #define SQ_L14 0x0000000e 7585 #define SQ_L15 0x0000000f 7586 7587 /* 7588 * VALUE_SQ_OP_SOP2 value 7589 */ 7590 7591 #define SQ_S_ADD_U32 0x00000000 7592 #define SQ_S_SUB_U32 0x00000001 7593 #define SQ_S_ADD_I32 0x00000002 7594 #define SQ_S_SUB_I32 0x00000003 7595 #define SQ_S_ADDC_U32 0x00000004 7596 #define SQ_S_SUBB_U32 0x00000005 7597 #define SQ_S_MIN_I32 0x00000006 7598 #define SQ_S_MIN_U32 0x00000007 7599 #define SQ_S_MAX_I32 0x00000008 7600 #define SQ_S_MAX_U32 0x00000009 7601 #define SQ_S_CSELECT_B32 0x0000000a 7602 #define SQ_S_CSELECT_B64 0x0000000b 7603 #define SQ_S_AND_B32 0x0000000c 7604 #define SQ_S_AND_B64 0x0000000d 7605 #define SQ_S_OR_B32 0x0000000e 7606 #define SQ_S_OR_B64 0x0000000f 7607 #define SQ_S_XOR_B32 0x00000010 7608 #define SQ_S_XOR_B64 0x00000011 7609 #define SQ_S_ANDN2_B32 0x00000012 7610 #define SQ_S_ANDN2_B64 0x00000013 7611 #define SQ_S_ORN2_B32 0x00000014 7612 #define SQ_S_ORN2_B64 0x00000015 7613 #define SQ_S_NAND_B32 0x00000016 7614 #define SQ_S_NAND_B64 0x00000017 7615 #define SQ_S_NOR_B32 0x00000018 7616 #define SQ_S_NOR_B64 0x00000019 7617 #define SQ_S_XNOR_B32 0x0000001a 7618 #define SQ_S_XNOR_B64 0x0000001b 7619 #define SQ_S_LSHL_B32 0x0000001c 7620 #define SQ_S_LSHL_B64 0x0000001d 7621 #define SQ_S_LSHR_B32 0x0000001e 7622 #define SQ_S_LSHR_B64 0x0000001f 7623 #define SQ_S_ASHR_I32 0x00000020 7624 #define SQ_S_ASHR_I64 0x00000021 7625 #define SQ_S_BFM_B32 0x00000022 7626 #define SQ_S_BFM_B64 0x00000023 7627 #define SQ_S_MUL_I32 0x00000024 7628 #define SQ_S_BFE_U32 0x00000025 7629 #define SQ_S_BFE_I32 0x00000026 7630 #define SQ_S_BFE_U64 0x00000027 7631 #define SQ_S_BFE_I64 0x00000028 7632 #define SQ_S_CBRANCH_G_FORK 0x00000029 7633 #define SQ_S_ABSDIFF_I32 0x0000002a 7634 #define SQ_S_RFE_RESTORE_B64 0x0000002b 7635 #define SQ_S_MUL_HI_U32 0x0000002c 7636 #define SQ_S_MUL_HI_I32 0x0000002d 7637 #define SQ_S_LSHL1_ADD_U32 0x0000002e 7638 #define SQ_S_LSHL2_ADD_U32 0x0000002f 7639 #define SQ_S_LSHL3_ADD_U32 0x00000030 7640 #define SQ_S_LSHL4_ADD_U32 0x00000031 7641 #define SQ_S_PACK_LL_B32_B16 0x00000032 7642 #define SQ_S_PACK_LH_B32_B16 0x00000033 7643 #define SQ_S_PACK_HH_B32_B16 0x00000034 7644 7645 /* 7646 * VALUE_SQ_SDST_EXEC value 7647 */ 7648 7649 #define SQ_EXEC_LO 0x0000007e 7650 #define SQ_EXEC_HI 0x0000007f 7651 7652 /* 7653 * VALUE_SQ_SSRC_SPECIAL_POPS_EXITING_WAVE_ID value 7654 */ 7655 7656 #define SQ_SRC_POPS_EXITING_WAVE_ID 0x000000ef 7657 7658 /* 7659 * VALUE_SQ_COMPI value 7660 */ 7661 7662 #define SQ_F 0x00000000 7663 #define SQ_LT 0x00000001 7664 #define SQ_EQ 0x00000002 7665 #define SQ_LE 0x00000003 7666 #define SQ_GT 0x00000004 7667 #define SQ_NE 0x00000005 7668 #define SQ_GE 0x00000006 7669 #define SQ_T 0x00000007 7670 7671 /* 7672 * VALUE_SQ_SGPR value 7673 */ 7674 7675 #define SQ_SGPR0 0x00000000 7676 7677 /* 7678 * VALUE_SQ_CHAN value 7679 */ 7680 7681 #define SQ_CHAN_X 0x00000000 7682 #define SQ_CHAN_Y 0x00000001 7683 #define SQ_CHAN_Z 0x00000002 7684 #define SQ_CHAN_W 0x00000003 7685 7686 /* 7687 * VALUE_SQ_SSRC_SPECIAL_SDWA value 7688 */ 7689 7690 #define SQ_SRC_SDWA 0x000000f9 7691 7692 /* 7693 * VALUE_SQ_SSRC_SPECIAL_LIT value 7694 */ 7695 7696 #define SQ_SRC_LITERAL 0x000000ff 7697 7698 /* 7699 * VALUE_SQ_DPP_BOUND_CTRL value 7700 */ 7701 7702 #define SQ_DPP_BOUND_OFF 0x00000000 7703 #define SQ_DPP_BOUND_ZERO 0x00000001 7704 7705 /* 7706 * VALUE_SQ_GS_OP value 7707 */ 7708 7709 #define SQ_GS_OP_NOP 0x00000000 7710 #define SQ_GS_OP_CUT 0x00000001 7711 #define SQ_GS_OP_EMIT 0x00000002 7712 #define SQ_GS_OP_EMIT_CUT 0x00000003 7713 7714 /* 7715 * VALUE_SQ_OP_MTBUF value 7716 */ 7717 7718 #define SQ_TBUFFER_LOAD_FORMAT_X 0x00000000 7719 #define SQ_TBUFFER_LOAD_FORMAT_XY 0x00000001 7720 #define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x00000002 7721 #define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x00000003 7722 #define SQ_TBUFFER_STORE_FORMAT_X 0x00000004 7723 #define SQ_TBUFFER_STORE_FORMAT_XY 0x00000005 7724 #define SQ_TBUFFER_STORE_FORMAT_XYZ 0x00000006 7725 #define SQ_TBUFFER_STORE_FORMAT_XYZW 0x00000007 7726 #define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x00000008 7727 #define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x00000009 7728 #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a 7729 #define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b 7730 #define SQ_TBUFFER_STORE_FORMAT_D16_X 0x0000000c 7731 #define SQ_TBUFFER_STORE_FORMAT_D16_XY 0x0000000d 7732 #define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0x0000000e 7733 #define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0x0000000f 7734 7735 /* 7736 * VALUE_SQ_SSRC_SPECIAL_EXECZ value 7737 */ 7738 7739 #define SQ_SRC_EXECZ 0x000000fc 7740 7741 /* 7742 * VALUE_SQ_OP_VOP3P value 7743 */ 7744 7745 #define SQ_V_PK_MAD_I16 0x00000000 7746 #define SQ_V_PK_MUL_LO_U16 0x00000001 7747 #define SQ_V_PK_ADD_I16 0x00000002 7748 #define SQ_V_PK_SUB_I16 0x00000003 7749 #define SQ_V_PK_LSHLREV_B16 0x00000004 7750 #define SQ_V_PK_LSHRREV_B16 0x00000005 7751 #define SQ_V_PK_ASHRREV_I16 0x00000006 7752 #define SQ_V_PK_MAX_I16 0x00000007 7753 #define SQ_V_PK_MIN_I16 0x00000008 7754 #define SQ_V_PK_MAD_U16 0x00000009 7755 #define SQ_V_PK_ADD_U16 0x0000000a 7756 #define SQ_V_PK_SUB_U16 0x0000000b 7757 #define SQ_V_PK_MAX_U16 0x0000000c 7758 #define SQ_V_PK_MIN_U16 0x0000000d 7759 #define SQ_V_PK_MAD_F16 0x0000000e 7760 #define SQ_V_PK_ADD_F16 0x0000000f 7761 #define SQ_V_PK_MUL_F16 0x00000010 7762 #define SQ_V_PK_MIN_F16 0x00000011 7763 #define SQ_V_PK_MAX_F16 0x00000012 7764 #define SQ_V_MAD_MIX_F32 0x00000020 7765 #define SQ_V_MAD_MIXLO_F16 0x00000021 7766 #define SQ_V_MAD_MIXHI_F16 0x00000022 7767 7768 /* 7769 * VALUE_SQ_SYSMSG_OP value 7770 */ 7771 7772 #define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001 7773 #define SQ_SYSMSG_OP_REG_RD 0x00000002 7774 #define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x00000003 7775 #define SQ_SYSMSG_OP_TTRACE_PC 0x00000004 7776 #define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT 0x00000005 7777 #define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT 0x00000006 7778 7779 /* 7780 * VALUE_SQ_VCC value 7781 */ 7782 7783 #define SQ_VCC_ALL 0x00000000 7784 7785 /* 7786 * VALUE_SQ_OP_SMEM value 7787 */ 7788 7789 #define SQ_S_LOAD_DWORD 0x00000000 7790 #define SQ_S_LOAD_DWORDX2 0x00000001 7791 #define SQ_S_LOAD_DWORDX4 0x00000002 7792 #define SQ_S_LOAD_DWORDX8 0x00000003 7793 #define SQ_S_LOAD_DWORDX16 0x00000004 7794 #define SQ_S_SCRATCH_LOAD_DWORD 0x00000005 7795 #define SQ_S_SCRATCH_LOAD_DWORDX2 0x00000006 7796 #define SQ_S_SCRATCH_LOAD_DWORDX4 0x00000007 7797 #define SQ_S_BUFFER_LOAD_DWORD 0x00000008 7798 #define SQ_S_BUFFER_LOAD_DWORDX2 0x00000009 7799 #define SQ_S_BUFFER_LOAD_DWORDX4 0x0000000a 7800 #define SQ_S_BUFFER_LOAD_DWORDX8 0x0000000b 7801 #define SQ_S_BUFFER_LOAD_DWORDX16 0x0000000c 7802 #define SQ_S_STORE_DWORD 0x00000010 7803 #define SQ_S_STORE_DWORDX2 0x00000011 7804 #define SQ_S_STORE_DWORDX4 0x00000012 7805 #define SQ_S_SCRATCH_STORE_DWORD 0x00000015 7806 #define SQ_S_SCRATCH_STORE_DWORDX2 0x00000016 7807 #define SQ_S_SCRATCH_STORE_DWORDX4 0x00000017 7808 #define SQ_S_BUFFER_STORE_DWORD 0x00000018 7809 #define SQ_S_BUFFER_STORE_DWORDX2 0x00000019 7810 #define SQ_S_BUFFER_STORE_DWORDX4 0x0000001a 7811 #define SQ_S_DCACHE_INV 0x00000020 7812 #define SQ_S_DCACHE_WB 0x00000021 7813 #define SQ_S_DCACHE_INV_VOL 0x00000022 7814 #define SQ_S_DCACHE_WB_VOL 0x00000023 7815 #define SQ_S_MEMTIME 0x00000024 7816 #define SQ_S_MEMREALTIME 0x00000025 7817 #define SQ_S_ATC_PROBE 0x00000026 7818 #define SQ_S_ATC_PROBE_BUFFER 0x00000027 7819 #define SQ_S_BUFFER_ATOMIC_SWAP 0x00000040 7820 #define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x00000041 7821 #define SQ_S_BUFFER_ATOMIC_ADD 0x00000042 7822 #define SQ_S_BUFFER_ATOMIC_SUB 0x00000043 7823 #define SQ_S_BUFFER_ATOMIC_SMIN 0x00000044 7824 #define SQ_S_BUFFER_ATOMIC_UMIN 0x00000045 7825 #define SQ_S_BUFFER_ATOMIC_SMAX 0x00000046 7826 #define SQ_S_BUFFER_ATOMIC_UMAX 0x00000047 7827 #define SQ_S_BUFFER_ATOMIC_AND 0x00000048 7828 #define SQ_S_BUFFER_ATOMIC_OR 0x00000049 7829 #define SQ_S_BUFFER_ATOMIC_XOR 0x0000004a 7830 #define SQ_S_BUFFER_ATOMIC_INC 0x0000004b 7831 #define SQ_S_BUFFER_ATOMIC_DEC 0x0000004c 7832 #define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x00000060 7833 #define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x00000061 7834 #define SQ_S_BUFFER_ATOMIC_ADD_X2 0x00000062 7835 #define SQ_S_BUFFER_ATOMIC_SUB_X2 0x00000063 7836 #define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x00000064 7837 #define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x00000065 7838 #define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x00000066 7839 #define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x00000067 7840 #define SQ_S_BUFFER_ATOMIC_AND_X2 0x00000068 7841 #define SQ_S_BUFFER_ATOMIC_OR_X2 0x00000069 7842 #define SQ_S_BUFFER_ATOMIC_XOR_X2 0x0000006a 7843 #define SQ_S_BUFFER_ATOMIC_INC_X2 0x0000006b 7844 #define SQ_S_BUFFER_ATOMIC_DEC_X2 0x0000006c 7845 #define SQ_S_ATOMIC_SWAP 0x00000080 7846 #define SQ_S_ATOMIC_CMPSWAP 0x00000081 7847 #define SQ_S_ATOMIC_ADD 0x00000082 7848 #define SQ_S_ATOMIC_SUB 0x00000083 7849 #define SQ_S_ATOMIC_SMIN 0x00000084 7850 #define SQ_S_ATOMIC_UMIN 0x00000085 7851 #define SQ_S_ATOMIC_SMAX 0x00000086 7852 #define SQ_S_ATOMIC_UMAX 0x00000087 7853 #define SQ_S_ATOMIC_AND 0x00000088 7854 #define SQ_S_ATOMIC_OR 0x00000089 7855 #define SQ_S_ATOMIC_XOR 0x0000008a 7856 #define SQ_S_ATOMIC_INC 0x0000008b 7857 #define SQ_S_ATOMIC_DEC 0x0000008c 7858 #define SQ_S_ATOMIC_SWAP_X2 0x000000a0 7859 #define SQ_S_ATOMIC_CMPSWAP_X2 0x000000a1 7860 #define SQ_S_ATOMIC_ADD_X2 0x000000a2 7861 #define SQ_S_ATOMIC_SUB_X2 0x000000a3 7862 #define SQ_S_ATOMIC_SMIN_X2 0x000000a4 7863 #define SQ_S_ATOMIC_UMIN_X2 0x000000a5 7864 #define SQ_S_ATOMIC_SMAX_X2 0x000000a6 7865 #define SQ_S_ATOMIC_UMAX_X2 0x000000a7 7866 #define SQ_S_ATOMIC_AND_X2 0x000000a8 7867 #define SQ_S_ATOMIC_OR_X2 0x000000a9 7868 #define SQ_S_ATOMIC_XOR_X2 0x000000aa 7869 #define SQ_S_ATOMIC_INC_X2 0x000000ab 7870 #define SQ_S_ATOMIC_DEC_X2 0x000000ac 7871 7872 /* 7873 * VALUE_SQ_OP_DS value 7874 */ 7875 7876 #define SQ_DS_ADD_U32 0x00000000 7877 #define SQ_DS_SUB_U32 0x00000001 7878 #define SQ_DS_RSUB_U32 0x00000002 7879 #define SQ_DS_INC_U32 0x00000003 7880 #define SQ_DS_DEC_U32 0x00000004 7881 #define SQ_DS_MIN_I32 0x00000005 7882 #define SQ_DS_MAX_I32 0x00000006 7883 #define SQ_DS_MIN_U32 0x00000007 7884 #define SQ_DS_MAX_U32 0x00000008 7885 #define SQ_DS_AND_B32 0x00000009 7886 #define SQ_DS_OR_B32 0x0000000a 7887 #define SQ_DS_XOR_B32 0x0000000b 7888 #define SQ_DS_MSKOR_B32 0x0000000c 7889 #define SQ_DS_WRITE_B32 0x0000000d 7890 #define SQ_DS_WRITE2_B32 0x0000000e 7891 #define SQ_DS_WRITE2ST64_B32 0x0000000f 7892 #define SQ_DS_CMPST_B32 0x00000010 7893 #define SQ_DS_CMPST_F32 0x00000011 7894 #define SQ_DS_MIN_F32 0x00000012 7895 #define SQ_DS_MAX_F32 0x00000013 7896 #define SQ_DS_NOP 0x00000014 7897 #define SQ_DS_ADD_F32 0x00000015 7898 #define SQ_DS_WRITE_ADDTID_B32 0x0000001d 7899 #define SQ_DS_WRITE_B8 0x0000001e 7900 #define SQ_DS_WRITE_B16 0x0000001f 7901 #define SQ_DS_ADD_RTN_U32 0x00000020 7902 #define SQ_DS_SUB_RTN_U32 0x00000021 7903 #define SQ_DS_RSUB_RTN_U32 0x00000022 7904 #define SQ_DS_INC_RTN_U32 0x00000023 7905 #define SQ_DS_DEC_RTN_U32 0x00000024 7906 #define SQ_DS_MIN_RTN_I32 0x00000025 7907 #define SQ_DS_MAX_RTN_I32 0x00000026 7908 #define SQ_DS_MIN_RTN_U32 0x00000027 7909 #define SQ_DS_MAX_RTN_U32 0x00000028 7910 #define SQ_DS_AND_RTN_B32 0x00000029 7911 #define SQ_DS_OR_RTN_B32 0x0000002a 7912 #define SQ_DS_XOR_RTN_B32 0x0000002b 7913 #define SQ_DS_MSKOR_RTN_B32 0x0000002c 7914 #define SQ_DS_WRXCHG_RTN_B32 0x0000002d 7915 #define SQ_DS_WRXCHG2_RTN_B32 0x0000002e 7916 #define SQ_DS_WRXCHG2ST64_RTN_B32 0x0000002f 7917 #define SQ_DS_CMPST_RTN_B32 0x00000030 7918 #define SQ_DS_CMPST_RTN_F32 0x00000031 7919 #define SQ_DS_MIN_RTN_F32 0x00000032 7920 #define SQ_DS_MAX_RTN_F32 0x00000033 7921 #define SQ_DS_WRAP_RTN_B32 0x00000034 7922 #define SQ_DS_ADD_RTN_F32 0x00000035 7923 #define SQ_DS_READ_B32 0x00000036 7924 #define SQ_DS_READ2_B32 0x00000037 7925 #define SQ_DS_READ2ST64_B32 0x00000038 7926 #define SQ_DS_READ_I8 0x00000039 7927 #define SQ_DS_READ_U8 0x0000003a 7928 #define SQ_DS_READ_I16 0x0000003b 7929 #define SQ_DS_READ_U16 0x0000003c 7930 #define SQ_DS_SWIZZLE_B32 0x0000003d 7931 #define SQ_DS_PERMUTE_B32 0x0000003e 7932 #define SQ_DS_BPERMUTE_B32 0x0000003f 7933 #define SQ_DS_ADD_U64 0x00000040 7934 #define SQ_DS_SUB_U64 0x00000041 7935 #define SQ_DS_RSUB_U64 0x00000042 7936 #define SQ_DS_INC_U64 0x00000043 7937 #define SQ_DS_DEC_U64 0x00000044 7938 #define SQ_DS_MIN_I64 0x00000045 7939 #define SQ_DS_MAX_I64 0x00000046 7940 #define SQ_DS_MIN_U64 0x00000047 7941 #define SQ_DS_MAX_U64 0x00000048 7942 #define SQ_DS_AND_B64 0x00000049 7943 #define SQ_DS_OR_B64 0x0000004a 7944 #define SQ_DS_XOR_B64 0x0000004b 7945 #define SQ_DS_MSKOR_B64 0x0000004c 7946 #define SQ_DS_WRITE_B64 0x0000004d 7947 #define SQ_DS_WRITE2_B64 0x0000004e 7948 #define SQ_DS_WRITE2ST64_B64 0x0000004f 7949 #define SQ_DS_CMPST_B64 0x00000050 7950 #define SQ_DS_CMPST_F64 0x00000051 7951 #define SQ_DS_MIN_F64 0x00000052 7952 #define SQ_DS_MAX_F64 0x00000053 7953 #define SQ_DS_ADD_RTN_U64 0x00000060 7954 #define SQ_DS_SUB_RTN_U64 0x00000061 7955 #define SQ_DS_RSUB_RTN_U64 0x00000062 7956 #define SQ_DS_INC_RTN_U64 0x00000063 7957 #define SQ_DS_DEC_RTN_U64 0x00000064 7958 #define SQ_DS_MIN_RTN_I64 0x00000065 7959 #define SQ_DS_MAX_RTN_I64 0x00000066 7960 #define SQ_DS_MIN_RTN_U64 0x00000067 7961 #define SQ_DS_MAX_RTN_U64 0x00000068 7962 #define SQ_DS_AND_RTN_B64 0x00000069 7963 #define SQ_DS_OR_RTN_B64 0x0000006a 7964 #define SQ_DS_XOR_RTN_B64 0x0000006b 7965 #define SQ_DS_MSKOR_RTN_B64 0x0000006c 7966 #define SQ_DS_WRXCHG_RTN_B64 0x0000006d 7967 #define SQ_DS_WRXCHG2_RTN_B64 0x0000006e 7968 #define SQ_DS_WRXCHG2ST64_RTN_B64 0x0000006f 7969 #define SQ_DS_CMPST_RTN_B64 0x00000070 7970 #define SQ_DS_CMPST_RTN_F64 0x00000071 7971 #define SQ_DS_MIN_RTN_F64 0x00000072 7972 #define SQ_DS_MAX_RTN_F64 0x00000073 7973 #define SQ_DS_READ_B64 0x00000076 7974 #define SQ_DS_READ2_B64 0x00000077 7975 #define SQ_DS_READ2ST64_B64 0x00000078 7976 #define SQ_DS_CONDXCHG32_RTN_B64 0x0000007e 7977 #define SQ_DS_ADD_SRC2_U32 0x00000080 7978 #define SQ_DS_SUB_SRC2_U32 0x00000081 7979 #define SQ_DS_RSUB_SRC2_U32 0x00000082 7980 #define SQ_DS_INC_SRC2_U32 0x00000083 7981 #define SQ_DS_DEC_SRC2_U32 0x00000084 7982 #define SQ_DS_MIN_SRC2_I32 0x00000085 7983 #define SQ_DS_MAX_SRC2_I32 0x00000086 7984 #define SQ_DS_MIN_SRC2_U32 0x00000087 7985 #define SQ_DS_MAX_SRC2_U32 0x00000088 7986 #define SQ_DS_AND_SRC2_B32 0x00000089 7987 #define SQ_DS_OR_SRC2_B32 0x0000008a 7988 #define SQ_DS_XOR_SRC2_B32 0x0000008b 7989 #define SQ_DS_WRITE_SRC2_B32 0x0000008d 7990 #define SQ_DS_MIN_SRC2_F32 0x00000092 7991 #define SQ_DS_MAX_SRC2_F32 0x00000093 7992 #define SQ_DS_ADD_SRC2_F32 0x00000095 7993 #define SQ_DS_GWS_SEMA_RELEASE_ALL 0x00000098 7994 #define SQ_DS_GWS_INIT 0x00000099 7995 #define SQ_DS_GWS_SEMA_V 0x0000009a 7996 #define SQ_DS_GWS_SEMA_BR 0x0000009b 7997 #define SQ_DS_GWS_SEMA_P 0x0000009c 7998 #define SQ_DS_GWS_BARRIER 0x0000009d 7999 #define SQ_DS_READ_ADDTID_B32 0x000000b6 8000 #define SQ_DS_CONSUME 0x000000bd 8001 #define SQ_DS_APPEND 0x000000be 8002 #define SQ_DS_ORDERED_COUNT 0x000000bf 8003 #define SQ_DS_ADD_SRC2_U64 0x000000c0 8004 #define SQ_DS_SUB_SRC2_U64 0x000000c1 8005 #define SQ_DS_RSUB_SRC2_U64 0x000000c2 8006 #define SQ_DS_INC_SRC2_U64 0x000000c3 8007 #define SQ_DS_DEC_SRC2_U64 0x000000c4 8008 #define SQ_DS_MIN_SRC2_I64 0x000000c5 8009 #define SQ_DS_MAX_SRC2_I64 0x000000c6 8010 #define SQ_DS_MIN_SRC2_U64 0x000000c7 8011 #define SQ_DS_MAX_SRC2_U64 0x000000c8 8012 #define SQ_DS_AND_SRC2_B64 0x000000c9 8013 #define SQ_DS_OR_SRC2_B64 0x000000ca 8014 #define SQ_DS_XOR_SRC2_B64 0x000000cb 8015 #define SQ_DS_WRITE_SRC2_B64 0x000000cd 8016 #define SQ_DS_MIN_SRC2_F64 0x000000d2 8017 #define SQ_DS_MAX_SRC2_F64 0x000000d3 8018 #define SQ_DS_WRITE_B96 0x000000de 8019 #define SQ_DS_WRITE_B128 0x000000df 8020 #define SQ_DS_CONDXCHG32_RTN_B128 0x000000fd 8021 #define SQ_DS_READ_B96 0x000000fe 8022 #define SQ_DS_READ_B128 0x000000ff 8023 8024 /* 8025 * VALUE_SQ_SDWA_SEL value 8026 */ 8027 8028 #define SQ_SDWA_BYTE_0 0x00000000 8029 #define SQ_SDWA_BYTE_1 0x00000001 8030 #define SQ_SDWA_BYTE_2 0x00000002 8031 #define SQ_SDWA_BYTE_3 0x00000003 8032 #define SQ_SDWA_WORD_0 0x00000004 8033 #define SQ_SDWA_WORD_1 0x00000005 8034 #define SQ_SDWA_DWORD 0x00000006 8035 8036 /* 8037 * VALUE_SQ_OP_VOP2 value 8038 */ 8039 8040 #define SQ_V_CNDMASK_B32 0x00000000 8041 #define SQ_V_ADD_F32 0x00000001 8042 #define SQ_V_SUB_F32 0x00000002 8043 #define SQ_V_SUBREV_F32 0x00000003 8044 #define SQ_V_MUL_LEGACY_F32 0x00000004 8045 #define SQ_V_MUL_F32 0x00000005 8046 #define SQ_V_MUL_I32_I24 0x00000006 8047 #define SQ_V_MUL_HI_I32_I24 0x00000007 8048 #define SQ_V_MUL_U32_U24 0x00000008 8049 #define SQ_V_MUL_HI_U32_U24 0x00000009 8050 #define SQ_V_MIN_F32 0x0000000a 8051 #define SQ_V_MAX_F32 0x0000000b 8052 #define SQ_V_MIN_I32 0x0000000c 8053 #define SQ_V_MAX_I32 0x0000000d 8054 #define SQ_V_MIN_U32 0x0000000e 8055 #define SQ_V_MAX_U32 0x0000000f 8056 #define SQ_V_LSHRREV_B32 0x00000010 8057 #define SQ_V_ASHRREV_I32 0x00000011 8058 #define SQ_V_LSHLREV_B32 0x00000012 8059 #define SQ_V_AND_B32 0x00000013 8060 #define SQ_V_OR_B32 0x00000014 8061 #define SQ_V_XOR_B32 0x00000015 8062 #define SQ_V_MAC_F32 0x00000016 8063 #define SQ_V_MADMK_F32 0x00000017 8064 #define SQ_V_MADAK_F32 0x00000018 8065 #define SQ_V_ADD_CO_U32 0x00000019 8066 #define SQ_V_SUB_CO_U32 0x0000001a 8067 #define SQ_V_SUBREV_CO_U32 0x0000001b 8068 #define SQ_V_ADDC_CO_U32 0x0000001c 8069 #define SQ_V_SUBB_CO_U32 0x0000001d 8070 #define SQ_V_SUBBREV_CO_U32 0x0000001e 8071 #define SQ_V_ADD_F16 0x0000001f 8072 #define SQ_V_SUB_F16 0x00000020 8073 #define SQ_V_SUBREV_F16 0x00000021 8074 #define SQ_V_MUL_F16 0x00000022 8075 #define SQ_V_MAC_F16 0x00000023 8076 #define SQ_V_MADMK_F16 0x00000024 8077 #define SQ_V_MADAK_F16 0x00000025 8078 #define SQ_V_ADD_U16 0x00000026 8079 #define SQ_V_SUB_U16 0x00000027 8080 #define SQ_V_SUBREV_U16 0x00000028 8081 #define SQ_V_MUL_LO_U16 0x00000029 8082 #define SQ_V_LSHLREV_B16 0x0000002a 8083 #define SQ_V_LSHRREV_B16 0x0000002b 8084 #define SQ_V_ASHRREV_I16 0x0000002c 8085 #define SQ_V_MAX_F16 0x0000002d 8086 #define SQ_V_MIN_F16 0x0000002e 8087 #define SQ_V_MAX_U16 0x0000002f 8088 #define SQ_V_MAX_I16 0x00000030 8089 #define SQ_V_MIN_U16 0x00000031 8090 #define SQ_V_MIN_I16 0x00000032 8091 #define SQ_V_LDEXP_F16 0x00000033 8092 #define SQ_V_ADD_U32 0x00000034 8093 #define SQ_V_SUB_U32 0x00000035 8094 #define SQ_V_SUBREV_U32 0x00000036 8095 8096 /* 8097 * VALUE_SQ_SRC_VGPR value 8098 */ 8099 8100 #define SQ_SRC_VGPR0 0x00000100 8101 8102 /* 8103 * VALUE_SQ_OP_SOPP value 8104 */ 8105 8106 #define SQ_S_NOP 0x00000000 8107 #define SQ_S_ENDPGM 0x00000001 8108 #define SQ_S_BRANCH 0x00000002 8109 #define SQ_S_WAKEUP 0x00000003 8110 #define SQ_S_CBRANCH_SCC0 0x00000004 8111 #define SQ_S_CBRANCH_SCC1 0x00000005 8112 #define SQ_S_CBRANCH_VCCZ 0x00000006 8113 #define SQ_S_CBRANCH_VCCNZ 0x00000007 8114 #define SQ_S_CBRANCH_EXECZ 0x00000008 8115 #define SQ_S_CBRANCH_EXECNZ 0x00000009 8116 #define SQ_S_BARRIER 0x0000000a 8117 #define SQ_S_SETKILL 0x0000000b 8118 #define SQ_S_WAITCNT 0x0000000c 8119 #define SQ_S_SETHALT 0x0000000d 8120 #define SQ_S_SLEEP 0x0000000e 8121 #define SQ_S_SETPRIO 0x0000000f 8122 #define SQ_S_SENDMSG 0x00000010 8123 #define SQ_S_SENDMSGHALT 0x00000011 8124 #define SQ_S_TRAP 0x00000012 8125 #define SQ_S_ICACHE_INV 0x00000013 8126 #define SQ_S_INCPERFLEVEL 0x00000014 8127 #define SQ_S_DECPERFLEVEL 0x00000015 8128 #define SQ_S_TTRACEDATA 0x00000016 8129 #define SQ_S_CBRANCH_CDBGSYS 0x00000017 8130 #define SQ_S_CBRANCH_CDBGUSER 0x00000018 8131 #define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x00000019 8132 #define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x0000001a 8133 #define SQ_S_ENDPGM_SAVED 0x0000001b 8134 #define SQ_S_SET_GPR_IDX_OFF 0x0000001c 8135 #define SQ_S_SET_GPR_IDX_MODE 0x0000001d 8136 #define SQ_S_ENDPGM_ORDERED_PS_DONE 0x0000001e 8137 8138 /* 8139 * VALUE_SQ_XNACK_MASK_LOHI value 8140 */ 8141 8142 #define SQ_XNACK_MASK_LO 0x00000068 8143 #define SQ_XNACK_MASK_HI 0x00000069 8144 8145 /* 8146 * VALUE_SQ_SDWA_UNUSED value 8147 */ 8148 8149 #define SQ_SDWA_UNUSED_PAD 0x00000000 8150 #define SQ_SDWA_UNUSED_SEXT 0x00000001 8151 #define SQ_SDWA_UNUSED_PRESERVE 0x00000002 8152 8153 /* 8154 * VALUE_SQ_OP_FLAT value 8155 */ 8156 8157 #define SQ_FLAT_LOAD_UBYTE 0x00000010 8158 #define SQ_FLAT_LOAD_SBYTE 0x00000011 8159 #define SQ_FLAT_LOAD_USHORT 0x00000012 8160 #define SQ_FLAT_LOAD_SSHORT 0x00000013 8161 #define SQ_FLAT_LOAD_DWORD 0x00000014 8162 #define SQ_FLAT_LOAD_DWORDX2 0x00000015 8163 #define SQ_FLAT_LOAD_DWORDX3 0x00000016 8164 #define SQ_FLAT_LOAD_DWORDX4 0x00000017 8165 #define SQ_FLAT_STORE_BYTE 0x00000018 8166 #define SQ_FLAT_STORE_SHORT 0x0000001a 8167 #define SQ_FLAT_STORE_DWORD 0x0000001c 8168 #define SQ_FLAT_STORE_DWORDX2 0x0000001d 8169 #define SQ_FLAT_STORE_DWORDX3 0x0000001e 8170 #define SQ_FLAT_STORE_DWORDX4 0x0000001f 8171 #define SQ_FLAT_ATOMIC_SWAP 0x00000040 8172 #define SQ_FLAT_ATOMIC_CMPSWAP 0x00000041 8173 #define SQ_FLAT_ATOMIC_ADD 0x00000042 8174 #define SQ_FLAT_ATOMIC_SUB 0x00000043 8175 #define SQ_FLAT_ATOMIC_SMIN 0x00000044 8176 #define SQ_FLAT_ATOMIC_UMIN 0x00000045 8177 #define SQ_FLAT_ATOMIC_SMAX 0x00000046 8178 #define SQ_FLAT_ATOMIC_UMAX 0x00000047 8179 #define SQ_FLAT_ATOMIC_AND 0x00000048 8180 #define SQ_FLAT_ATOMIC_OR 0x00000049 8181 #define SQ_FLAT_ATOMIC_XOR 0x0000004a 8182 #define SQ_FLAT_ATOMIC_INC 0x0000004b 8183 #define SQ_FLAT_ATOMIC_DEC 0x0000004c 8184 #define SQ_FLAT_ATOMIC_SWAP_X2 0x00000060 8185 #define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x00000061 8186 #define SQ_FLAT_ATOMIC_ADD_X2 0x00000062 8187 #define SQ_FLAT_ATOMIC_SUB_X2 0x00000063 8188 #define SQ_FLAT_ATOMIC_SMIN_X2 0x00000064 8189 #define SQ_FLAT_ATOMIC_UMIN_X2 0x00000065 8190 #define SQ_FLAT_ATOMIC_SMAX_X2 0x00000066 8191 #define SQ_FLAT_ATOMIC_UMAX_X2 0x00000067 8192 #define SQ_FLAT_ATOMIC_AND_X2 0x00000068 8193 #define SQ_FLAT_ATOMIC_OR_X2 0x00000069 8194 #define SQ_FLAT_ATOMIC_XOR_X2 0x0000006a 8195 #define SQ_FLAT_ATOMIC_INC_X2 0x0000006b 8196 #define SQ_FLAT_ATOMIC_DEC_X2 0x0000006c 8197 8198 /* 8199 * VALUE_SQ_OP_SOPC value 8200 */ 8201 8202 #define SQ_S_CMP_EQ_I32 0x00000000 8203 #define SQ_S_CMP_LG_I32 0x00000001 8204 #define SQ_S_CMP_GT_I32 0x00000002 8205 #define SQ_S_CMP_GE_I32 0x00000003 8206 #define SQ_S_CMP_LT_I32 0x00000004 8207 #define SQ_S_CMP_LE_I32 0x00000005 8208 #define SQ_S_CMP_EQ_U32 0x00000006 8209 #define SQ_S_CMP_LG_U32 0x00000007 8210 #define SQ_S_CMP_GT_U32 0x00000008 8211 #define SQ_S_CMP_GE_U32 0x00000009 8212 #define SQ_S_CMP_LT_U32 0x0000000a 8213 #define SQ_S_CMP_LE_U32 0x0000000b 8214 #define SQ_S_BITCMP0_B32 0x0000000c 8215 #define SQ_S_BITCMP1_B32 0x0000000d 8216 #define SQ_S_BITCMP0_B64 0x0000000e 8217 #define SQ_S_BITCMP1_B64 0x0000000f 8218 #define SQ_S_SETVSKIP 0x00000010 8219 #define SQ_S_SET_GPR_IDX_ON 0x00000011 8220 #define SQ_S_CMP_EQ_U64 0x00000012 8221 #define SQ_S_CMP_LG_U64 0x00000013 8222 8223 /* 8224 * VALUE_SQ_PARAM value 8225 */ 8226 8227 #define SQ_PARAM_P10 0x00000000 8228 #define SQ_PARAM_P20 0x00000001 8229 #define SQ_PARAM_P0 0x00000002 8230 8231 /* 8232 * VALUE_SQ_OP_FLAT_SCRATCH value 8233 */ 8234 8235 #define SQ_SCRATCH_LOAD_UBYTE 0x00000010 8236 #define SQ_SCRATCH_LOAD_SBYTE 0x00000011 8237 #define SQ_SCRATCH_LOAD_USHORT 0x00000012 8238 #define SQ_SCRATCH_LOAD_SSHORT 0x00000013 8239 #define SQ_SCRATCH_LOAD_DWORD 0x00000014 8240 #define SQ_SCRATCH_LOAD_DWORDX2 0x00000015 8241 #define SQ_SCRATCH_LOAD_DWORDX3 0x00000016 8242 #define SQ_SCRATCH_LOAD_DWORDX4 0x00000017 8243 #define SQ_SCRATCH_STORE_BYTE 0x00000018 8244 #define SQ_SCRATCH_STORE_SHORT 0x0000001a 8245 #define SQ_SCRATCH_STORE_DWORD 0x0000001c 8246 #define SQ_SCRATCH_STORE_DWORDX2 0x0000001d 8247 #define SQ_SCRATCH_STORE_DWORDX3 0x0000001e 8248 #define SQ_SCRATCH_STORE_DWORDX4 0x0000001f 8249 8250 /* 8251 * VALUE_SQ_SEG value 8252 */ 8253 8254 #define SQ_FLAT 0x00000000 8255 #define SQ_SCRATCH 0x00000001 8256 #define SQ_GLOBAL 0x00000002 8257 8258 /* 8259 * VALUE_SQ_SSRC_0_63_INLINES value 8260 */ 8261 8262 #define SQ_SRC_0 0x00000080 8263 #define SQ_SRC_1_INT 0x00000081 8264 #define SQ_SRC_2_INT 0x00000082 8265 #define SQ_SRC_3_INT 0x00000083 8266 #define SQ_SRC_4_INT 0x00000084 8267 #define SQ_SRC_5_INT 0x00000085 8268 #define SQ_SRC_6_INT 0x00000086 8269 #define SQ_SRC_7_INT 0x00000087 8270 #define SQ_SRC_8_INT 0x00000088 8271 #define SQ_SRC_9_INT 0x00000089 8272 #define SQ_SRC_10_INT 0x0000008a 8273 #define SQ_SRC_11_INT 0x0000008b 8274 #define SQ_SRC_12_INT 0x0000008c 8275 #define SQ_SRC_13_INT 0x0000008d 8276 #define SQ_SRC_14_INT 0x0000008e 8277 #define SQ_SRC_15_INT 0x0000008f 8278 #define SQ_SRC_16_INT 0x00000090 8279 #define SQ_SRC_17_INT 0x00000091 8280 #define SQ_SRC_18_INT 0x00000092 8281 #define SQ_SRC_19_INT 0x00000093 8282 #define SQ_SRC_20_INT 0x00000094 8283 #define SQ_SRC_21_INT 0x00000095 8284 #define SQ_SRC_22_INT 0x00000096 8285 #define SQ_SRC_23_INT 0x00000097 8286 #define SQ_SRC_24_INT 0x00000098 8287 #define SQ_SRC_25_INT 0x00000099 8288 #define SQ_SRC_26_INT 0x0000009a 8289 #define SQ_SRC_27_INT 0x0000009b 8290 #define SQ_SRC_28_INT 0x0000009c 8291 #define SQ_SRC_29_INT 0x0000009d 8292 #define SQ_SRC_30_INT 0x0000009e 8293 #define SQ_SRC_31_INT 0x0000009f 8294 #define SQ_SRC_32_INT 0x000000a0 8295 #define SQ_SRC_33_INT 0x000000a1 8296 #define SQ_SRC_34_INT 0x000000a2 8297 #define SQ_SRC_35_INT 0x000000a3 8298 #define SQ_SRC_36_INT 0x000000a4 8299 #define SQ_SRC_37_INT 0x000000a5 8300 #define SQ_SRC_38_INT 0x000000a6 8301 #define SQ_SRC_39_INT 0x000000a7 8302 #define SQ_SRC_40_INT 0x000000a8 8303 #define SQ_SRC_41_INT 0x000000a9 8304 #define SQ_SRC_42_INT 0x000000aa 8305 #define SQ_SRC_43_INT 0x000000ab 8306 #define SQ_SRC_44_INT 0x000000ac 8307 #define SQ_SRC_45_INT 0x000000ad 8308 #define SQ_SRC_46_INT 0x000000ae 8309 #define SQ_SRC_47_INT 0x000000af 8310 #define SQ_SRC_48_INT 0x000000b0 8311 #define SQ_SRC_49_INT 0x000000b1 8312 #define SQ_SRC_50_INT 0x000000b2 8313 #define SQ_SRC_51_INT 0x000000b3 8314 #define SQ_SRC_52_INT 0x000000b4 8315 #define SQ_SRC_53_INT 0x000000b5 8316 #define SQ_SRC_54_INT 0x000000b6 8317 #define SQ_SRC_55_INT 0x000000b7 8318 #define SQ_SRC_56_INT 0x000000b8 8319 #define SQ_SRC_57_INT 0x000000b9 8320 #define SQ_SRC_58_INT 0x000000ba 8321 #define SQ_SRC_59_INT 0x000000bb 8322 #define SQ_SRC_60_INT 0x000000bc 8323 #define SQ_SRC_61_INT 0x000000bd 8324 #define SQ_SRC_62_INT 0x000000be 8325 #define SQ_SRC_63_INT 0x000000bf 8326 8327 /* 8328 * VALUE_SQ_CNT value 8329 */ 8330 8331 #define SQ_CNT1 0x00000000 8332 #define SQ_CNT2 0x00000001 8333 #define SQ_CNT3 0x00000002 8334 #define SQ_CNT4 0x00000003 8335 8336 /******************************************************* 8337 * DIDT Enums 8338 *******************************************************/ 8339 8340 /******************************************************* 8341 * SX Enums 8342 *******************************************************/ 8343 8344 /* 8345 * SX_BLEND_OPT enum 8346 */ 8347 8348 typedef enum SX_BLEND_OPT { 8349 BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000, 8350 BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001, 8351 BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002, 8352 BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003, 8353 BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004, 8354 BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005, 8355 BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006, 8356 BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007, 8357 } SX_BLEND_OPT; 8358 8359 /* 8360 * SX_OPT_COMB_FCN enum 8361 */ 8362 8363 typedef enum SX_OPT_COMB_FCN { 8364 OPT_COMB_NONE = 0x00000000, 8365 OPT_COMB_ADD = 0x00000001, 8366 OPT_COMB_SUBTRACT = 0x00000002, 8367 OPT_COMB_MIN = 0x00000003, 8368 OPT_COMB_MAX = 0x00000004, 8369 OPT_COMB_REVSUBTRACT = 0x00000005, 8370 OPT_COMB_BLEND_DISABLED = 0x00000006, 8371 OPT_COMB_SAFE_ADD = 0x00000007, 8372 } SX_OPT_COMB_FCN; 8373 8374 /* 8375 * SX_DOWNCONVERT_FORMAT enum 8376 */ 8377 8378 typedef enum SX_DOWNCONVERT_FORMAT { 8379 SX_RT_EXPORT_NO_CONVERSION = 0x00000000, 8380 SX_RT_EXPORT_32_R = 0x00000001, 8381 SX_RT_EXPORT_32_A = 0x00000002, 8382 SX_RT_EXPORT_10_11_11 = 0x00000003, 8383 SX_RT_EXPORT_2_10_10_10 = 0x00000004, 8384 SX_RT_EXPORT_8_8_8_8 = 0x00000005, 8385 SX_RT_EXPORT_5_6_5 = 0x00000006, 8386 SX_RT_EXPORT_1_5_5_5 = 0x00000007, 8387 SX_RT_EXPORT_4_4_4_4 = 0x00000008, 8388 SX_RT_EXPORT_16_16_GR = 0x00000009, 8389 SX_RT_EXPORT_16_16_AR = 0x0000000a, 8390 } SX_DOWNCONVERT_FORMAT; 8391 8392 /* 8393 * SX_PERFCOUNTER_VALS enum 8394 */ 8395 8396 typedef enum SX_PERFCOUNTER_VALS { 8397 SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000, 8398 SX_PERF_SEL_PA_REQ = 0x00000001, 8399 SX_PERF_SEL_PA_POS = 0x00000002, 8400 SX_PERF_SEL_CLOCK = 0x00000003, 8401 SX_PERF_SEL_GATE_EN1 = 0x00000004, 8402 SX_PERF_SEL_GATE_EN2 = 0x00000005, 8403 SX_PERF_SEL_GATE_EN3 = 0x00000006, 8404 SX_PERF_SEL_GATE_EN4 = 0x00000007, 8405 SX_PERF_SEL_SH_POS_STARVE = 0x00000008, 8406 SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009, 8407 SX_PERF_SEL_SH_POS_STALL = 0x0000000a, 8408 SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b, 8409 SX_PERF_SEL_DB0_PIXELS = 0x0000000c, 8410 SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d, 8411 SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e, 8412 SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f, 8413 SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010, 8414 SX_PERF_SEL_DB1_PIXELS = 0x00000011, 8415 SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012, 8416 SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013, 8417 SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014, 8418 SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015, 8419 SX_PERF_SEL_DB2_PIXELS = 0x00000016, 8420 SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017, 8421 SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018, 8422 SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019, 8423 SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a, 8424 SX_PERF_SEL_DB3_PIXELS = 0x0000001b, 8425 SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c, 8426 SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d, 8427 SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e, 8428 SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f, 8429 SX_PERF_SEL_COL_BUSY = 0x00000020, 8430 SX_PERF_SEL_POS_BUSY = 0x00000021, 8431 SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 0x00000022, 8432 SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 0x00000023, 8433 SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 0x00000024, 8434 SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 0x00000025, 8435 SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 0x00000026, 8436 SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 0x00000027, 8437 SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 0x00000028, 8438 SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 0x00000029, 8439 SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 0x0000002a, 8440 SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 0x0000002b, 8441 SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 0x0000002c, 8442 SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 0x0000002d, 8443 SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 0x0000002e, 8444 SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 0x0000002f, 8445 SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 0x00000030, 8446 SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 0x00000031, 8447 SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 0x00000032, 8448 SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 0x00000033, 8449 SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 0x00000034, 8450 SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 0x00000035, 8451 SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 0x00000036, 8452 SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 0x00000037, 8453 SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 0x00000038, 8454 SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 0x00000039, 8455 SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 0x0000003a, 8456 SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 0x0000003b, 8457 SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 0x0000003c, 8458 SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 0x0000003d, 8459 SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 0x0000003e, 8460 SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 0x0000003f, 8461 SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 0x00000040, 8462 SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 0x00000041, 8463 SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 0x00000042, 8464 SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 0x00000043, 8465 SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 0x00000044, 8466 SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 0x00000045, 8467 SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 0x00000046, 8468 SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 0x00000047, 8469 SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 0x00000048, 8470 SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 0x00000049, 8471 SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 0x0000004a, 8472 SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 0x0000004b, 8473 SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 0x0000004c, 8474 SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 0x0000004d, 8475 SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 0x0000004e, 8476 SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 0x0000004f, 8477 SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 0x00000050, 8478 SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 0x00000051, 8479 SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 0x00000052, 8480 SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 0x00000053, 8481 SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 0x00000054, 8482 SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 0x00000055, 8483 SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 0x00000056, 8484 SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 0x00000057, 8485 SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 0x00000058, 8486 SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 0x00000059, 8487 SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 0x0000005a, 8488 SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 0x0000005b, 8489 SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 0x0000005c, 8490 SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 0x0000005d, 8491 SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 0x0000005e, 8492 SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 0x0000005f, 8493 SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 0x00000060, 8494 SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 0x00000061, 8495 SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 0x00000062, 8496 SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 0x00000063, 8497 SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 0x00000064, 8498 SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 0x00000065, 8499 SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 0x00000066, 8500 SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 0x00000067, 8501 SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 0x00000068, 8502 SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 0x00000069, 8503 SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 0x0000006a, 8504 SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 0x0000006b, 8505 SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 0x0000006c, 8506 SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 0x0000006d, 8507 SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 0x0000006e, 8508 SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 0x0000006f, 8509 SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 0x00000070, 8510 SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 0x00000071, 8511 SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 0x00000072, 8512 SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 0x00000073, 8513 SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 0x00000074, 8514 SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 0x00000075, 8515 SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 0x00000076, 8516 SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 0x00000077, 8517 SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 0x00000078, 8518 SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 0x00000079, 8519 SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 0x0000007a, 8520 SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 0x0000007b, 8521 SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 0x0000007c, 8522 SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 0x0000007d, 8523 SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 0x0000007e, 8524 SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 0x0000007f, 8525 SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 0x00000080, 8526 SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 0x00000081, 8527 SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 0x00000082, 8528 SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 0x00000083, 8529 SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 0x00000084, 8530 SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 0x00000085, 8531 SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 0x00000086, 8532 SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 0x00000087, 8533 SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 0x00000088, 8534 SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 0x00000089, 8535 SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 0x0000008a, 8536 SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 0x0000008b, 8537 SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 0x0000008c, 8538 SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 0x0000008d, 8539 SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 0x0000008e, 8540 SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 0x0000008f, 8541 SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 0x00000090, 8542 SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 0x00000091, 8543 SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 0x00000092, 8544 SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 0x00000093, 8545 SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 0x00000094, 8546 SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 0x00000095, 8547 SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 0x00000096, 8548 SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 0x00000097, 8549 SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 0x00000098, 8550 SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 0x00000099, 8551 SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 0x0000009a, 8552 SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 0x0000009b, 8553 SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 0x0000009c, 8554 SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 0x0000009d, 8555 SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 0x0000009e, 8556 SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 0x0000009f, 8557 SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 0x000000a0, 8558 SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 0x000000a1, 8559 SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 0x000000a2, 8560 SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 0x000000a3, 8561 SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 0x000000a4, 8562 SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 0x000000a5, 8563 SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 0x000000a6, 8564 SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 0x000000a7, 8565 SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 0x000000a8, 8566 SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 0x000000a9, 8567 SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 0x000000aa, 8568 SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 0x000000ab, 8569 SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 0x000000ac, 8570 SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 0x000000ad, 8571 SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 0x000000ae, 8572 SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 0x000000af, 8573 SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 0x000000b0, 8574 SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 0x000000b1, 8575 SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 0x000000b2, 8576 SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 0x000000b3, 8577 SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 0x000000b4, 8578 SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 0x000000b5, 8579 SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 0x000000b6, 8580 SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 0x000000b7, 8581 SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 0x000000b8, 8582 SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 0x000000b9, 8583 SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 0x000000ba, 8584 SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 0x000000bb, 8585 SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 0x000000bc, 8586 SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 0x000000bd, 8587 SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 0x000000be, 8588 SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 0x000000bf, 8589 SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 0x000000c0, 8590 SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 0x000000c1, 8591 SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 0x000000c2, 8592 SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 0x000000c3, 8593 SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 0x000000c4, 8594 SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 0x000000c5, 8595 } SX_PERFCOUNTER_VALS; 8596 8597 /******************************************************* 8598 * DB Enums 8599 *******************************************************/ 8600 8601 /* 8602 * ForceControl enum 8603 */ 8604 8605 typedef enum ForceControl { 8606 FORCE_OFF = 0x00000000, 8607 FORCE_ENABLE = 0x00000001, 8608 FORCE_DISABLE = 0x00000002, 8609 FORCE_RESERVED = 0x00000003, 8610 } ForceControl; 8611 8612 /* 8613 * ZSamplePosition enum 8614 */ 8615 8616 typedef enum ZSamplePosition { 8617 Z_SAMPLE_CENTER = 0x00000000, 8618 Z_SAMPLE_CENTROID = 0x00000001, 8619 } ZSamplePosition; 8620 8621 /* 8622 * ZOrder enum 8623 */ 8624 8625 typedef enum ZOrder { 8626 LATE_Z = 0x00000000, 8627 EARLY_Z_THEN_LATE_Z = 0x00000001, 8628 RE_Z = 0x00000002, 8629 EARLY_Z_THEN_RE_Z = 0x00000003, 8630 } ZOrder; 8631 8632 /* 8633 * ZpassControl enum 8634 */ 8635 8636 typedef enum ZpassControl { 8637 ZPASS_DISABLE = 0x00000000, 8638 ZPASS_SAMPLES = 0x00000001, 8639 ZPASS_PIXELS = 0x00000002, 8640 } ZpassControl; 8641 8642 /* 8643 * ZModeForce enum 8644 */ 8645 8646 typedef enum ZModeForce { 8647 NO_FORCE = 0x00000000, 8648 FORCE_EARLY_Z = 0x00000001, 8649 FORCE_LATE_Z = 0x00000002, 8650 FORCE_RE_Z = 0x00000003, 8651 } ZModeForce; 8652 8653 /* 8654 * ZLimitSumm enum 8655 */ 8656 8657 typedef enum ZLimitSumm { 8658 FORCE_SUMM_OFF = 0x00000000, 8659 FORCE_SUMM_MINZ = 0x00000001, 8660 FORCE_SUMM_MAXZ = 0x00000002, 8661 FORCE_SUMM_BOTH = 0x00000003, 8662 } ZLimitSumm; 8663 8664 /* 8665 * CompareFrag enum 8666 */ 8667 8668 typedef enum CompareFrag { 8669 FRAG_NEVER = 0x00000000, 8670 FRAG_LESS = 0x00000001, 8671 FRAG_EQUAL = 0x00000002, 8672 FRAG_LEQUAL = 0x00000003, 8673 FRAG_GREATER = 0x00000004, 8674 FRAG_NOTEQUAL = 0x00000005, 8675 FRAG_GEQUAL = 0x00000006, 8676 FRAG_ALWAYS = 0x00000007, 8677 } CompareFrag; 8678 8679 /* 8680 * StencilOp enum 8681 */ 8682 8683 typedef enum StencilOp { 8684 STENCIL_KEEP = 0x00000000, 8685 STENCIL_ZERO = 0x00000001, 8686 STENCIL_ONES = 0x00000002, 8687 STENCIL_REPLACE_TEST = 0x00000003, 8688 STENCIL_REPLACE_OP = 0x00000004, 8689 STENCIL_ADD_CLAMP = 0x00000005, 8690 STENCIL_SUB_CLAMP = 0x00000006, 8691 STENCIL_INVERT = 0x00000007, 8692 STENCIL_ADD_WRAP = 0x00000008, 8693 STENCIL_SUB_WRAP = 0x00000009, 8694 STENCIL_AND = 0x0000000a, 8695 STENCIL_OR = 0x0000000b, 8696 STENCIL_XOR = 0x0000000c, 8697 STENCIL_NAND = 0x0000000d, 8698 STENCIL_NOR = 0x0000000e, 8699 STENCIL_XNOR = 0x0000000f, 8700 } StencilOp; 8701 8702 /* 8703 * ConservativeZExport enum 8704 */ 8705 8706 typedef enum ConservativeZExport { 8707 EXPORT_ANY_Z = 0x00000000, 8708 EXPORT_LESS_THAN_Z = 0x00000001, 8709 EXPORT_GREATER_THAN_Z = 0x00000002, 8710 EXPORT_RESERVED = 0x00000003, 8711 } ConservativeZExport; 8712 8713 /* 8714 * DbPSLControl enum 8715 */ 8716 8717 typedef enum DbPSLControl { 8718 PSLC_AUTO = 0x00000000, 8719 PSLC_ON_HANG_ONLY = 0x00000001, 8720 PSLC_ASAP = 0x00000002, 8721 PSLC_COUNTDOWN = 0x00000003, 8722 } DbPSLControl; 8723 8724 /* 8725 * DbPRTFaultBehavior enum 8726 */ 8727 8728 typedef enum DbPRTFaultBehavior { 8729 FAULT_ZERO = 0x00000000, 8730 FAULT_ONE = 0x00000001, 8731 FAULT_FAIL = 0x00000002, 8732 FAULT_PASS = 0x00000003, 8733 } DbPRTFaultBehavior; 8734 8735 /* 8736 * PerfCounter_Vals enum 8737 */ 8738 8739 typedef enum PerfCounter_Vals { 8740 DB_PERF_SEL_SC_DB_tile_sends = 0x00000000, 8741 DB_PERF_SEL_SC_DB_tile_busy = 0x00000001, 8742 DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002, 8743 DB_PERF_SEL_SC_DB_tile_events = 0x00000003, 8744 DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004, 8745 DB_PERF_SEL_SC_DB_tile_covered = 0x00000005, 8746 DB_PERF_SEL_hiz_tc_read_starved = 0x00000006, 8747 DB_PERF_SEL_hiz_tc_write_stall = 0x00000007, 8748 DB_PERF_SEL_hiz_qtiles_culled = 0x00000008, 8749 DB_PERF_SEL_his_qtiles_culled = 0x00000009, 8750 DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a, 8751 DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b, 8752 DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c, 8753 DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d, 8754 DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e, 8755 DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f, 8756 DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010, 8757 DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011, 8758 DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012, 8759 DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013, 8760 DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014, 8761 DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015, 8762 DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016, 8763 DB_PERF_SEL_SC_DB_quad_sends = 0x00000017, 8764 DB_PERF_SEL_SC_DB_quad_busy = 0x00000018, 8765 DB_PERF_SEL_SC_DB_quad_squads = 0x00000019, 8766 DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a, 8767 DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b, 8768 DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c, 8769 DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d, 8770 DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e, 8771 DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f, 8772 DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020, 8773 DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021, 8774 DB_PERF_SEL_DB_CB_tile_sends = 0x00000022, 8775 DB_PERF_SEL_DB_CB_tile_busy = 0x00000023, 8776 DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024, 8777 DB_PERF_SEL_SX_DB_quad_sends = 0x00000025, 8778 DB_PERF_SEL_SX_DB_quad_busy = 0x00000026, 8779 DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027, 8780 DB_PERF_SEL_SX_DB_quad_quads = 0x00000028, 8781 DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029, 8782 DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a, 8783 DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b, 8784 DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c, 8785 DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d, 8786 DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e, 8787 DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f, 8788 DB_PERF_SEL_tile_rd_sends = 0x00000030, 8789 DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031, 8790 DB_PERF_SEL_quad_rd_sends = 0x00000032, 8791 DB_PERF_SEL_quad_rd_busy = 0x00000033, 8792 DB_PERF_SEL_quad_rd_mi_stall = 0x00000034, 8793 DB_PERF_SEL_quad_rd_rw_collision = 0x00000035, 8794 DB_PERF_SEL_quad_rd_tag_stall = 0x00000036, 8795 DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037, 8796 DB_PERF_SEL_quad_rd_panic = 0x00000038, 8797 DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039, 8798 DB_PERF_SEL_quad_rdret_sends = 0x0000003a, 8799 DB_PERF_SEL_quad_rdret_busy = 0x0000003b, 8800 DB_PERF_SEL_tile_wr_sends = 0x0000003c, 8801 DB_PERF_SEL_tile_wr_acks = 0x0000003d, 8802 DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e, 8803 DB_PERF_SEL_quad_wr_sends = 0x0000003f, 8804 DB_PERF_SEL_quad_wr_busy = 0x00000040, 8805 DB_PERF_SEL_quad_wr_mi_stall = 0x00000041, 8806 DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042, 8807 DB_PERF_SEL_quad_wr_acks = 0x00000043, 8808 DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044, 8809 DB_PERF_SEL_Tile_Cache_misses = 0x00000045, 8810 DB_PERF_SEL_Tile_Cache_hits = 0x00000046, 8811 DB_PERF_SEL_Tile_Cache_flushes = 0x00000047, 8812 DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048, 8813 DB_PERF_SEL_Tile_Cache_starves = 0x00000049, 8814 DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a, 8815 DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b, 8816 DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c, 8817 DB_PERF_SEL_tcp_preloader_reads = 0x0000004d, 8818 DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e, 8819 DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f, 8820 DB_PERF_SEL_tcp_preloader_flushes = 0x00000050, 8821 DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051, 8822 DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052, 8823 DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053, 8824 DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054, 8825 DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055, 8826 DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056, 8827 DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057, 8828 DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058, 8829 DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059, 8830 DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a, 8831 DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b, 8832 DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c, 8833 DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d, 8834 DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e, 8835 DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f, 8836 DB_PERF_SEL_Stencil_Cache_hits = 0x00000060, 8837 DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061, 8838 DB_PERF_SEL_Stencil_Cache_starves = 0x00000062, 8839 DB_PERF_SEL_Stencil_Cache_frees = 0x00000063, 8840 DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064, 8841 DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065, 8842 DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066, 8843 DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067, 8844 DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068, 8845 DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069, 8846 DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a, 8847 DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b, 8848 DB_PERF_SEL_Z_Cache_frees = 0x0000006c, 8849 DB_PERF_SEL_Plane_Cache_misses = 0x0000006d, 8850 DB_PERF_SEL_Plane_Cache_hits = 0x0000006e, 8851 DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f, 8852 DB_PERF_SEL_Plane_Cache_starves = 0x00000070, 8853 DB_PERF_SEL_Plane_Cache_frees = 0x00000071, 8854 DB_PERF_SEL_flush_expanded_stencil = 0x00000072, 8855 DB_PERF_SEL_flush_compressed_stencil = 0x00000073, 8856 DB_PERF_SEL_flush_single_stencil = 0x00000074, 8857 DB_PERF_SEL_planes_flushed = 0x00000075, 8858 DB_PERF_SEL_flush_1plane = 0x00000076, 8859 DB_PERF_SEL_flush_2plane = 0x00000077, 8860 DB_PERF_SEL_flush_3plane = 0x00000078, 8861 DB_PERF_SEL_flush_4plane = 0x00000079, 8862 DB_PERF_SEL_flush_5plane = 0x0000007a, 8863 DB_PERF_SEL_flush_6plane = 0x0000007b, 8864 DB_PERF_SEL_flush_7plane = 0x0000007c, 8865 DB_PERF_SEL_flush_8plane = 0x0000007d, 8866 DB_PERF_SEL_flush_9plane = 0x0000007e, 8867 DB_PERF_SEL_flush_10plane = 0x0000007f, 8868 DB_PERF_SEL_flush_11plane = 0x00000080, 8869 DB_PERF_SEL_flush_12plane = 0x00000081, 8870 DB_PERF_SEL_flush_13plane = 0x00000082, 8871 DB_PERF_SEL_flush_14plane = 0x00000083, 8872 DB_PERF_SEL_flush_15plane = 0x00000084, 8873 DB_PERF_SEL_flush_16plane = 0x00000085, 8874 DB_PERF_SEL_flush_expanded_z = 0x00000086, 8875 DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087, 8876 DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088, 8877 DB_PERF_SEL_dk_tile_sends = 0x00000089, 8878 DB_PERF_SEL_dk_tile_busy = 0x0000008a, 8879 DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b, 8880 DB_PERF_SEL_dk_tile_stalls = 0x0000008c, 8881 DB_PERF_SEL_dk_squad_sends = 0x0000008d, 8882 DB_PERF_SEL_dk_squad_busy = 0x0000008e, 8883 DB_PERF_SEL_dk_squad_stalls = 0x0000008f, 8884 DB_PERF_SEL_Op_Pipe_Busy = 0x00000090, 8885 DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091, 8886 DB_PERF_SEL_qc_busy = 0x00000092, 8887 DB_PERF_SEL_qc_xfc = 0x00000093, 8888 DB_PERF_SEL_qc_conflicts = 0x00000094, 8889 DB_PERF_SEL_qc_full_stall = 0x00000095, 8890 DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096, 8891 DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097, 8892 DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098, 8893 DB_PERF_SEL_tl_busy = 0x00000099, 8894 DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a, 8895 DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b, 8896 DB_PERF_SEL_tl_stencil_stall = 0x0000009c, 8897 DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d, 8898 DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e, 8899 DB_PERF_SEL_tl_events = 0x0000009f, 8900 DB_PERF_SEL_tl_summarize_squads = 0x000000a0, 8901 DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1, 8902 DB_PERF_SEL_tl_expand_squads = 0x000000a2, 8903 DB_PERF_SEL_tl_preZ_squads = 0x000000a3, 8904 DB_PERF_SEL_tl_postZ_squads = 0x000000a4, 8905 DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5, 8906 DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6, 8907 DB_PERF_SEL_tl_tile_ops = 0x000000a7, 8908 DB_PERF_SEL_tl_in_xfc = 0x000000a8, 8909 DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9, 8910 DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa, 8911 DB_PERF_SEL_tl_out_xfc = 0x000000ab, 8912 DB_PERF_SEL_tl_out_squads = 0x000000ac, 8913 DB_PERF_SEL_zf_plane_multicycle = 0x000000ad, 8914 DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae, 8915 DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af, 8916 DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0, 8917 DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1, 8918 DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2, 8919 DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3, 8920 DB_PERF_SEL_ts_tc_update_stall = 0x000000b4, 8921 DB_PERF_SEL_sc_kick_start = 0x000000b5, 8922 DB_PERF_SEL_sc_kick_end = 0x000000b6, 8923 DB_PERF_SEL_clock_reg_active = 0x000000b7, 8924 DB_PERF_SEL_clock_main_active = 0x000000b8, 8925 DB_PERF_SEL_clock_mem_export_active = 0x000000b9, 8926 DB_PERF_SEL_esr_ps_out_busy = 0x000000ba, 8927 DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb, 8928 DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc, 8929 DB_PERF_SEL_etr_out_send = 0x000000bd, 8930 DB_PERF_SEL_etr_out_busy = 0x000000be, 8931 DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf, 8932 DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0, 8933 DB_PERF_SEL_etr_out_esr_stall = 0x000000c1, 8934 DB_PERF_SEL_esr_ps_sqq_busy = 0x000000c2, 8935 DB_PERF_SEL_esr_ps_sqq_stall = 0x000000c3, 8936 DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4, 8937 DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5, 8938 DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6, 8939 DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7, 8940 DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8, 8941 DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9, 8942 DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca, 8943 DB_PERF_SEL_postzl_se_busy = 0x000000cb, 8944 DB_PERF_SEL_postzl_se_stall = 0x000000cc, 8945 DB_PERF_SEL_postzl_partial_launch = 0x000000cd, 8946 DB_PERF_SEL_postzl_full_launch = 0x000000ce, 8947 DB_PERF_SEL_postzl_partial_waiting = 0x000000cf, 8948 DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0, 8949 DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1, 8950 DB_PEFF_SEL_prezl_tile_mem_stall = 0x000000d2, 8951 DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3, 8952 DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4, 8953 DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5, 8954 DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6, 8955 DB_PERF_SEL_mi_rdreq_busy = 0x000000d7, 8956 DB_PERF_SEL_mi_rdreq_stall = 0x000000d8, 8957 DB_PERF_SEL_mi_wrreq_busy = 0x000000d9, 8958 DB_PERF_SEL_mi_wrreq_stall = 0x000000da, 8959 DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db, 8960 DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc, 8961 DB_PERF_SEL_prezl_src_in_sends = 0x000000dd, 8962 DB_PERF_SEL_prezl_src_in_stall = 0x000000de, 8963 DB_PERF_SEL_prezl_src_in_squads = 0x000000df, 8964 DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0, 8965 DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1, 8966 DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2, 8967 DB_PERF_SEL_prezl_src_out_stall = 0x000000e3, 8968 DB_PERF_SEL_postzl_src_in_sends = 0x000000e4, 8969 DB_PERF_SEL_postzl_src_in_stall = 0x000000e5, 8970 DB_PERF_SEL_postzl_src_in_squads = 0x000000e6, 8971 DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7, 8972 DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8, 8973 DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9, 8974 DB_PERF_SEL_postzl_src_out_stall = 0x000000ea, 8975 DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb, 8976 DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec, 8977 DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed, 8978 DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee, 8979 DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef, 8980 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0, 8981 DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1, 8982 DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2, 8983 DB_PERF_SEL_depth_bounds_qtiles_culled = 0x000000f3, 8984 DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4, 8985 DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5, 8986 DB_PERF_SEL_flush_compressed = 0x000000f6, 8987 DB_PERF_SEL_flush_plane_le4 = 0x000000f7, 8988 DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8, 8989 DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9, 8990 DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa, 8991 DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb, 8992 DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc, 8993 DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd, 8994 DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe, 8995 DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff, 8996 DB_PERF_SEL_di_dt_stall = 0x00000100, 8997 DB_PERF_SEL_DB_SC_quad_double_quad = 0x00000101, 8998 DB_PERF_SEL_SX_DB_quad_export_quads = 0x00000102, 8999 DB_PERF_SEL_SX_DB_quad_double_format = 0x00000103, 9000 DB_PERF_SEL_SX_DB_quad_fast_format = 0x00000104, 9001 DB_PERF_SEL_SX_DB_quad_slow_format = 0x00000105, 9002 DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000106, 9003 DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000107, 9004 DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000108, 9005 DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000109, 9006 DB_PERF_SEL_CB_DB_rdreq_sends = 0x0000010a, 9007 DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010b, 9008 DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010c, 9009 DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010d, 9010 DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010e, 9011 DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010f, 9012 DB_PERF_SEL_DB_CB_wrret_ack = 0x00000110, 9013 DB_PERF_SEL_DB_CB_wrret_nack = 0x00000111, 9014 DB_PERF_SEL_DFSM_squads_in = 0x00000112, 9015 DB_PERF_SEL_DFSM_full_cleared_squads_out = 0x00000113, 9016 DB_PERF_SEL_DFSM_quads_in = 0x00000114, 9017 DB_PERF_SEL_DFSM_fully_cleared_quads_out = 0x00000115, 9018 DB_PERF_SEL_DFSM_lit_pixels_in = 0x00000116, 9019 DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 0x00000117, 9020 DB_PERF_SEL_DFSM_lit_samples_in = 0x00000118, 9021 DB_PERF_SEL_DFSM_lit_samples_out = 0x00000119, 9022 DB_PERF_SEL_DFSM_cycles_above_watermark = 0x0000011a, 9023 DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 0x0000011b, 9024 DB_PERF_SEL_DFSM_stalled_by_downstream = 0x0000011c, 9025 DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 0x0000011d, 9026 DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 0x0000011e, 9027 DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 0x0000011f, 9028 DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 0x00000120, 9029 } PerfCounter_Vals; 9030 9031 /* 9032 * RingCounterControl enum 9033 */ 9034 9035 typedef enum RingCounterControl { 9036 COUNTER_RING_SPLIT = 0x00000000, 9037 COUNTER_RING_0 = 0x00000001, 9038 COUNTER_RING_1 = 0x00000002, 9039 } RingCounterControl; 9040 9041 /* 9042 * DbMemArbWatermarks enum 9043 */ 9044 9045 typedef enum DbMemArbWatermarks { 9046 TRANSFERRED_64_BYTES = 0x00000000, 9047 TRANSFERRED_128_BYTES = 0x00000001, 9048 TRANSFERRED_256_BYTES = 0x00000002, 9049 TRANSFERRED_512_BYTES = 0x00000003, 9050 TRANSFERRED_1024_BYTES = 0x00000004, 9051 TRANSFERRED_2048_BYTES = 0x00000005, 9052 TRANSFERRED_4096_BYTES = 0x00000006, 9053 TRANSFERRED_8192_BYTES = 0x00000007, 9054 } DbMemArbWatermarks; 9055 9056 /* 9057 * DFSMFlushEvents enum 9058 */ 9059 9060 typedef enum DFSMFlushEvents { 9061 DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000, 9062 DB_FLUSH_AND_INV_DB_META = 0x00000001, 9063 DB_CACHE_FLUSH = 0x00000002, 9064 DB_CACHE_FLUSH_TS = 0x00000003, 9065 DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004, 9066 DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005, 9067 } DFSMFlushEvents; 9068 9069 /* 9070 * PixelPipeCounterId enum 9071 */ 9072 9073 typedef enum PixelPipeCounterId { 9074 PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000, 9075 PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001, 9076 PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002, 9077 PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003, 9078 PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004, 9079 PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005, 9080 PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006, 9081 PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007, 9082 } PixelPipeCounterId; 9083 9084 /* 9085 * PixelPipeStride enum 9086 */ 9087 9088 typedef enum PixelPipeStride { 9089 PIXEL_PIPE_STRIDE_32_BITS = 0x00000000, 9090 PIXEL_PIPE_STRIDE_64_BITS = 0x00000001, 9091 PIXEL_PIPE_STRIDE_128_BITS = 0x00000002, 9092 PIXEL_PIPE_STRIDE_256_BITS = 0x00000003, 9093 } PixelPipeStride; 9094 9095 /******************************************************* 9096 * TA Enums 9097 *******************************************************/ 9098 9099 /* 9100 * TEX_BORDER_COLOR_TYPE enum 9101 */ 9102 9103 typedef enum TEX_BORDER_COLOR_TYPE { 9104 TEX_BorderColor_TransparentBlack = 0x00000000, 9105 TEX_BorderColor_OpaqueBlack = 0x00000001, 9106 TEX_BorderColor_OpaqueWhite = 0x00000002, 9107 TEX_BorderColor_Register = 0x00000003, 9108 } TEX_BORDER_COLOR_TYPE; 9109 9110 /* 9111 * TEX_CHROMA_KEY enum 9112 */ 9113 9114 typedef enum TEX_CHROMA_KEY { 9115 TEX_ChromaKey_Disabled = 0x00000000, 9116 TEX_ChromaKey_Kill = 0x00000001, 9117 TEX_ChromaKey_Blend = 0x00000002, 9118 TEX_ChromaKey_RESERVED_3 = 0x00000003, 9119 } TEX_CHROMA_KEY; 9120 9121 /* 9122 * TEX_CLAMP enum 9123 */ 9124 9125 typedef enum TEX_CLAMP { 9126 TEX_Clamp_Repeat = 0x00000000, 9127 TEX_Clamp_Mirror = 0x00000001, 9128 TEX_Clamp_ClampToLast = 0x00000002, 9129 TEX_Clamp_MirrorOnceToLast = 0x00000003, 9130 TEX_Clamp_ClampHalfToBorder = 0x00000004, 9131 TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005, 9132 TEX_Clamp_ClampToBorder = 0x00000006, 9133 TEX_Clamp_MirrorOnceToBorder = 0x00000007, 9134 } TEX_CLAMP; 9135 9136 /* 9137 * TEX_COORD_TYPE enum 9138 */ 9139 9140 typedef enum TEX_COORD_TYPE { 9141 TEX_CoordType_Unnormalized = 0x00000000, 9142 TEX_CoordType_Normalized = 0x00000001, 9143 } TEX_COORD_TYPE; 9144 9145 /* 9146 * TEX_DEPTH_COMPARE_FUNCTION enum 9147 */ 9148 9149 typedef enum TEX_DEPTH_COMPARE_FUNCTION { 9150 TEX_DepthCompareFunction_Never = 0x00000000, 9151 TEX_DepthCompareFunction_Less = 0x00000001, 9152 TEX_DepthCompareFunction_Equal = 0x00000002, 9153 TEX_DepthCompareFunction_LessEqual = 0x00000003, 9154 TEX_DepthCompareFunction_Greater = 0x00000004, 9155 TEX_DepthCompareFunction_NotEqual = 0x00000005, 9156 TEX_DepthCompareFunction_GreaterEqual = 0x00000006, 9157 TEX_DepthCompareFunction_Always = 0x00000007, 9158 } TEX_DEPTH_COMPARE_FUNCTION; 9159 9160 /* 9161 * TEX_DIM enum 9162 */ 9163 9164 typedef enum TEX_DIM { 9165 TEX_Dim_1D = 0x00000000, 9166 TEX_Dim_2D = 0x00000001, 9167 TEX_Dim_3D = 0x00000002, 9168 TEX_Dim_CubeMap = 0x00000003, 9169 TEX_Dim_1DArray = 0x00000004, 9170 TEX_Dim_2DArray = 0x00000005, 9171 TEX_Dim_2D_MSAA = 0x00000006, 9172 TEX_Dim_2DArray_MSAA = 0x00000007, 9173 } TEX_DIM; 9174 9175 /* 9176 * TEX_FORMAT_COMP enum 9177 */ 9178 9179 typedef enum TEX_FORMAT_COMP { 9180 TEX_FormatComp_Unsigned = 0x00000000, 9181 TEX_FormatComp_Signed = 0x00000001, 9182 TEX_FormatComp_UnsignedBiased = 0x00000002, 9183 TEX_FormatComp_RESERVED_3 = 0x00000003, 9184 } TEX_FORMAT_COMP; 9185 9186 /* 9187 * TEX_MAX_ANISO_RATIO enum 9188 */ 9189 9190 typedef enum TEX_MAX_ANISO_RATIO { 9191 TEX_MaxAnisoRatio_1to1 = 0x00000000, 9192 TEX_MaxAnisoRatio_2to1 = 0x00000001, 9193 TEX_MaxAnisoRatio_4to1 = 0x00000002, 9194 TEX_MaxAnisoRatio_8to1 = 0x00000003, 9195 TEX_MaxAnisoRatio_16to1 = 0x00000004, 9196 TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005, 9197 TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006, 9198 TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007, 9199 } TEX_MAX_ANISO_RATIO; 9200 9201 /* 9202 * TEX_MIP_FILTER enum 9203 */ 9204 9205 typedef enum TEX_MIP_FILTER { 9206 TEX_MipFilter_None = 0x00000000, 9207 TEX_MipFilter_Point = 0x00000001, 9208 TEX_MipFilter_Linear = 0x00000002, 9209 TEX_MipFilter_Point_Aniso_Adj = 0x00000003, 9210 } TEX_MIP_FILTER; 9211 9212 /* 9213 * TEX_REQUEST_SIZE enum 9214 */ 9215 9216 typedef enum TEX_REQUEST_SIZE { 9217 TEX_RequestSize_32B = 0x00000000, 9218 TEX_RequestSize_64B = 0x00000001, 9219 TEX_RequestSize_128B = 0x00000002, 9220 TEX_RequestSize_2X64B = 0x00000003, 9221 } TEX_REQUEST_SIZE; 9222 9223 /* 9224 * TEX_SAMPLER_TYPE enum 9225 */ 9226 9227 typedef enum TEX_SAMPLER_TYPE { 9228 TEX_SamplerType_Invalid = 0x00000000, 9229 TEX_SamplerType_Valid = 0x00000001, 9230 } TEX_SAMPLER_TYPE; 9231 9232 /* 9233 * TEX_XY_FILTER enum 9234 */ 9235 9236 typedef enum TEX_XY_FILTER { 9237 TEX_XYFilter_Point = 0x00000000, 9238 TEX_XYFilter_Linear = 0x00000001, 9239 TEX_XYFilter_AnisoPoint = 0x00000002, 9240 TEX_XYFilter_AnisoLinear = 0x00000003, 9241 } TEX_XY_FILTER; 9242 9243 /* 9244 * TEX_Z_FILTER enum 9245 */ 9246 9247 typedef enum TEX_Z_FILTER { 9248 TEX_ZFilter_None = 0x00000000, 9249 TEX_ZFilter_Point = 0x00000001, 9250 TEX_ZFilter_Linear = 0x00000002, 9251 TEX_ZFilter_RESERVED_3 = 0x00000003, 9252 } TEX_Z_FILTER; 9253 9254 /* 9255 * VTX_CLAMP enum 9256 */ 9257 9258 typedef enum VTX_CLAMP { 9259 VTX_Clamp_ClampToZero = 0x00000000, 9260 VTX_Clamp_ClampToNAN = 0x00000001, 9261 } VTX_CLAMP; 9262 9263 /* 9264 * VTX_FETCH_TYPE enum 9265 */ 9266 9267 typedef enum VTX_FETCH_TYPE { 9268 VTX_FetchType_VertexData = 0x00000000, 9269 VTX_FetchType_InstanceData = 0x00000001, 9270 VTX_FetchType_NoIndexOffset = 0x00000002, 9271 VTX_FetchType_RESERVED_3 = 0x00000003, 9272 } VTX_FETCH_TYPE; 9273 9274 /* 9275 * VTX_FORMAT_COMP_ALL enum 9276 */ 9277 9278 typedef enum VTX_FORMAT_COMP_ALL { 9279 VTX_FormatCompAll_Unsigned = 0x00000000, 9280 VTX_FormatCompAll_Signed = 0x00000001, 9281 } VTX_FORMAT_COMP_ALL; 9282 9283 /* 9284 * VTX_MEM_REQUEST_SIZE enum 9285 */ 9286 9287 typedef enum VTX_MEM_REQUEST_SIZE { 9288 VTX_MemRequestSize_32B = 0x00000000, 9289 VTX_MemRequestSize_64B = 0x00000001, 9290 } VTX_MEM_REQUEST_SIZE; 9291 9292 /* 9293 * TVX_DATA_FORMAT enum 9294 */ 9295 9296 typedef enum TVX_DATA_FORMAT { 9297 TVX_FMT_INVALID = 0x00000000, 9298 TVX_FMT_8 = 0x00000001, 9299 TVX_FMT_4_4 = 0x00000002, 9300 TVX_FMT_3_3_2 = 0x00000003, 9301 TVX_FMT_RESERVED_4 = 0x00000004, 9302 TVX_FMT_16 = 0x00000005, 9303 TVX_FMT_16_FLOAT = 0x00000006, 9304 TVX_FMT_8_8 = 0x00000007, 9305 TVX_FMT_5_6_5 = 0x00000008, 9306 TVX_FMT_6_5_5 = 0x00000009, 9307 TVX_FMT_1_5_5_5 = 0x0000000a, 9308 TVX_FMT_4_4_4_4 = 0x0000000b, 9309 TVX_FMT_5_5_5_1 = 0x0000000c, 9310 TVX_FMT_32 = 0x0000000d, 9311 TVX_FMT_32_FLOAT = 0x0000000e, 9312 TVX_FMT_16_16 = 0x0000000f, 9313 TVX_FMT_16_16_FLOAT = 0x00000010, 9314 TVX_FMT_8_24 = 0x00000011, 9315 TVX_FMT_8_24_FLOAT = 0x00000012, 9316 TVX_FMT_24_8 = 0x00000013, 9317 TVX_FMT_24_8_FLOAT = 0x00000014, 9318 TVX_FMT_10_11_11 = 0x00000015, 9319 TVX_FMT_10_11_11_FLOAT = 0x00000016, 9320 TVX_FMT_11_11_10 = 0x00000017, 9321 TVX_FMT_11_11_10_FLOAT = 0x00000018, 9322 TVX_FMT_2_10_10_10 = 0x00000019, 9323 TVX_FMT_8_8_8_8 = 0x0000001a, 9324 TVX_FMT_10_10_10_2 = 0x0000001b, 9325 TVX_FMT_X24_8_32_FLOAT = 0x0000001c, 9326 TVX_FMT_32_32 = 0x0000001d, 9327 TVX_FMT_32_32_FLOAT = 0x0000001e, 9328 TVX_FMT_16_16_16_16 = 0x0000001f, 9329 TVX_FMT_16_16_16_16_FLOAT = 0x00000020, 9330 TVX_FMT_RESERVED_33 = 0x00000021, 9331 TVX_FMT_32_32_32_32 = 0x00000022, 9332 TVX_FMT_32_32_32_32_FLOAT = 0x00000023, 9333 TVX_FMT_RESERVED_36 = 0x00000024, 9334 TVX_FMT_1 = 0x00000025, 9335 TVX_FMT_1_REVERSED = 0x00000026, 9336 TVX_FMT_GB_GR = 0x00000027, 9337 TVX_FMT_BG_RG = 0x00000028, 9338 TVX_FMT_32_AS_8 = 0x00000029, 9339 TVX_FMT_32_AS_8_8 = 0x0000002a, 9340 TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b, 9341 TVX_FMT_8_8_8 = 0x0000002c, 9342 TVX_FMT_16_16_16 = 0x0000002d, 9343 TVX_FMT_16_16_16_FLOAT = 0x0000002e, 9344 TVX_FMT_32_32_32 = 0x0000002f, 9345 TVX_FMT_32_32_32_FLOAT = 0x00000030, 9346 TVX_FMT_BC1 = 0x00000031, 9347 TVX_FMT_BC2 = 0x00000032, 9348 TVX_FMT_BC3 = 0x00000033, 9349 TVX_FMT_BC4 = 0x00000034, 9350 TVX_FMT_BC5 = 0x00000035, 9351 TVX_FMT_APC0 = 0x00000036, 9352 TVX_FMT_APC1 = 0x00000037, 9353 TVX_FMT_APC2 = 0x00000038, 9354 TVX_FMT_APC3 = 0x00000039, 9355 TVX_FMT_APC4 = 0x0000003a, 9356 TVX_FMT_APC5 = 0x0000003b, 9357 TVX_FMT_APC6 = 0x0000003c, 9358 TVX_FMT_APC7 = 0x0000003d, 9359 TVX_FMT_CTX1 = 0x0000003e, 9360 TVX_FMT_RESERVED_63 = 0x0000003f, 9361 } TVX_DATA_FORMAT; 9362 9363 /* 9364 * TVX_DST_SEL enum 9365 */ 9366 9367 typedef enum TVX_DST_SEL { 9368 TVX_DstSel_X = 0x00000000, 9369 TVX_DstSel_Y = 0x00000001, 9370 TVX_DstSel_Z = 0x00000002, 9371 TVX_DstSel_W = 0x00000003, 9372 TVX_DstSel_0f = 0x00000004, 9373 TVX_DstSel_1f = 0x00000005, 9374 TVX_DstSel_RESERVED_6 = 0x00000006, 9375 TVX_DstSel_Mask = 0x00000007, 9376 } TVX_DST_SEL; 9377 9378 /* 9379 * TVX_ENDIAN_SWAP enum 9380 */ 9381 9382 typedef enum TVX_ENDIAN_SWAP { 9383 TVX_EndianSwap_None = 0x00000000, 9384 TVX_EndianSwap_8in16 = 0x00000001, 9385 TVX_EndianSwap_8in32 = 0x00000002, 9386 TVX_EndianSwap_8in64 = 0x00000003, 9387 } TVX_ENDIAN_SWAP; 9388 9389 /* 9390 * TVX_INST enum 9391 */ 9392 9393 typedef enum TVX_INST { 9394 TVX_Inst_NormalVertexFetch = 0x00000000, 9395 TVX_Inst_SemanticVertexFetch = 0x00000001, 9396 TVX_Inst_RESERVED_2 = 0x00000002, 9397 TVX_Inst_LD = 0x00000003, 9398 TVX_Inst_GetTextureResInfo = 0x00000004, 9399 TVX_Inst_GetNumberOfSamples = 0x00000005, 9400 TVX_Inst_GetLOD = 0x00000006, 9401 TVX_Inst_GetGradientsH = 0x00000007, 9402 TVX_Inst_GetGradientsV = 0x00000008, 9403 TVX_Inst_SetTextureOffsets = 0x00000009, 9404 TVX_Inst_KeepGradients = 0x0000000a, 9405 TVX_Inst_SetGradientsH = 0x0000000b, 9406 TVX_Inst_SetGradientsV = 0x0000000c, 9407 TVX_Inst_Pass = 0x0000000d, 9408 TVX_Inst_GetBufferResInfo = 0x0000000e, 9409 TVX_Inst_RESERVED_15 = 0x0000000f, 9410 TVX_Inst_Sample = 0x00000010, 9411 TVX_Inst_Sample_L = 0x00000011, 9412 TVX_Inst_Sample_LB = 0x00000012, 9413 TVX_Inst_Sample_LZ = 0x00000013, 9414 TVX_Inst_Sample_G = 0x00000014, 9415 TVX_Inst_Gather4 = 0x00000015, 9416 TVX_Inst_Sample_G_LB = 0x00000016, 9417 TVX_Inst_Gather4_O = 0x00000017, 9418 TVX_Inst_Sample_C = 0x00000018, 9419 TVX_Inst_Sample_C_L = 0x00000019, 9420 TVX_Inst_Sample_C_LB = 0x0000001a, 9421 TVX_Inst_Sample_C_LZ = 0x0000001b, 9422 TVX_Inst_Sample_C_G = 0x0000001c, 9423 TVX_Inst_Gather4_C = 0x0000001d, 9424 TVX_Inst_Sample_C_G_LB = 0x0000001e, 9425 TVX_Inst_Gather4_C_O = 0x0000001f, 9426 } TVX_INST; 9427 9428 /* 9429 * TVX_NUM_FORMAT_ALL enum 9430 */ 9431 9432 typedef enum TVX_NUM_FORMAT_ALL { 9433 TVX_NumFormatAll_Norm = 0x00000000, 9434 TVX_NumFormatAll_Int = 0x00000001, 9435 TVX_NumFormatAll_Scaled = 0x00000002, 9436 TVX_NumFormatAll_RESERVED_3 = 0x00000003, 9437 } TVX_NUM_FORMAT_ALL; 9438 9439 /* 9440 * TVX_SRC_SEL enum 9441 */ 9442 9443 typedef enum TVX_SRC_SEL { 9444 TVX_SrcSel_X = 0x00000000, 9445 TVX_SrcSel_Y = 0x00000001, 9446 TVX_SrcSel_Z = 0x00000002, 9447 TVX_SrcSel_W = 0x00000003, 9448 TVX_SrcSel_0f = 0x00000004, 9449 TVX_SrcSel_1f = 0x00000005, 9450 } TVX_SRC_SEL; 9451 9452 /* 9453 * TVX_SRF_MODE_ALL enum 9454 */ 9455 9456 typedef enum TVX_SRF_MODE_ALL { 9457 TVX_SRFModeAll_ZCMO = 0x00000000, 9458 TVX_SRFModeAll_NZ = 0x00000001, 9459 } TVX_SRF_MODE_ALL; 9460 9461 /* 9462 * TVX_TYPE enum 9463 */ 9464 9465 typedef enum TVX_TYPE { 9466 TVX_Type_InvalidTextureResource = 0x00000000, 9467 TVX_Type_InvalidVertexBuffer = 0x00000001, 9468 TVX_Type_ValidTextureResource = 0x00000002, 9469 TVX_Type_ValidVertexBuffer = 0x00000003, 9470 } TVX_TYPE; 9471 9472 /******************************************************* 9473 * PA Enums 9474 *******************************************************/ 9475 9476 /* 9477 * SU_PERFCNT_SEL enum 9478 */ 9479 9480 typedef enum SU_PERFCNT_SEL { 9481 PERF_PAPC_PASX_REQ = 0x00000000, 9482 PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001, 9483 PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002, 9484 PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003, 9485 PERF_PAPC_PASX_FIRST_DEAD = 0x00000004, 9486 PERF_PAPC_PASX_SECOND_DEAD = 0x00000005, 9487 PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006, 9488 PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007, 9489 PERF_PAPC_PA_INPUT_PRIM = 0x00000008, 9490 PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009, 9491 PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a, 9492 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b, 9493 PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c, 9494 PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d, 9495 PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e, 9496 PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f, 9497 PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010, 9498 PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011, 9499 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012, 9500 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013, 9501 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014, 9502 PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015, 9503 PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016, 9504 PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017, 9505 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018, 9506 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019, 9507 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a, 9508 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b, 9509 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c, 9510 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d, 9511 PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e, 9512 PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f, 9513 PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020, 9514 PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021, 9515 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022, 9516 PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023, 9517 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024, 9518 PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025, 9519 PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026, 9520 PERF_PAPC_CLSM_NULL_PRIM = 0x00000027, 9521 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028, 9522 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029, 9523 PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a, 9524 PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b, 9525 PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c, 9526 PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d, 9527 PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e, 9528 PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f, 9529 PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030, 9530 PERF_PAPC_SU_INPUT_PRIM = 0x00000031, 9531 PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032, 9532 PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033, 9533 PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034, 9534 PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035, 9535 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036, 9536 PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037, 9537 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038, 9538 PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039, 9539 PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a, 9540 PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b, 9541 PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c, 9542 PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d, 9543 PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e, 9544 PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f, 9545 PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040, 9546 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041, 9547 PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042, 9548 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043, 9549 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044, 9550 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045, 9551 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046, 9552 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047, 9553 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048, 9554 PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049, 9555 PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a, 9556 PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b, 9557 PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c, 9558 PERF_PAPC_PASX_REQ_IDLE = 0x0000004d, 9559 PERF_PAPC_PASX_REQ_BUSY = 0x0000004e, 9560 PERF_PAPC_PASX_REQ_STALLED = 0x0000004f, 9561 PERF_PAPC_PASX_REC_IDLE = 0x00000050, 9562 PERF_PAPC_PASX_REC_BUSY = 0x00000051, 9563 PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052, 9564 PERF_PAPC_PASX_REC_STALLED = 0x00000053, 9565 PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054, 9566 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055, 9567 PERF_PAPC_CCGSM_IDLE = 0x00000056, 9568 PERF_PAPC_CCGSM_BUSY = 0x00000057, 9569 PERF_PAPC_CCGSM_STALLED = 0x00000058, 9570 PERF_PAPC_CLPRIM_IDLE = 0x00000059, 9571 PERF_PAPC_CLPRIM_BUSY = 0x0000005a, 9572 PERF_PAPC_CLPRIM_STALLED = 0x0000005b, 9573 PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c, 9574 PERF_PAPC_CLIPSM_IDLE = 0x0000005d, 9575 PERF_PAPC_CLIPSM_BUSY = 0x0000005e, 9576 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f, 9577 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060, 9578 PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061, 9579 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062, 9580 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063, 9581 PERF_PAPC_CLIPGA_IDLE = 0x00000064, 9582 PERF_PAPC_CLIPGA_BUSY = 0x00000065, 9583 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066, 9584 PERF_PAPC_CLIPGA_STALLED = 0x00000067, 9585 PERF_PAPC_CLIP_IDLE = 0x00000068, 9586 PERF_PAPC_CLIP_BUSY = 0x00000069, 9587 PERF_PAPC_SU_IDLE = 0x0000006a, 9588 PERF_PAPC_SU_BUSY = 0x0000006b, 9589 PERF_PAPC_SU_STARVED_CLIP = 0x0000006c, 9590 PERF_PAPC_SU_STALLED_SC = 0x0000006d, 9591 PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e, 9592 PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f, 9593 PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070, 9594 PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071, 9595 PERF_PAPC_PASX_SE0_REQ = 0x00000072, 9596 PERF_PAPC_PASX_SE1_REQ = 0x00000073, 9597 PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074, 9598 PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075, 9599 PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076, 9600 PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077, 9601 PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078, 9602 PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079, 9603 PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a, 9604 PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b, 9605 PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c, 9606 PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d, 9607 PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e, 9608 PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f, 9609 PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080, 9610 PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081, 9611 PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082, 9612 PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083, 9613 PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084, 9614 PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085, 9615 PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086, 9616 PERF_PAPC_SU_CULLED_PRIM = 0x00000087, 9617 PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088, 9618 PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089, 9619 PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a, 9620 PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b, 9621 PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c, 9622 PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d, 9623 PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e, 9624 PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f, 9625 PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090, 9626 PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091, 9627 PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092, 9628 PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093, 9629 PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094, 9630 PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095, 9631 PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096, 9632 PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097, 9633 PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098, 9634 } SU_PERFCNT_SEL; 9635 9636 /* 9637 * SC_PERFCNT_SEL enum 9638 */ 9639 9640 typedef enum SC_PERFCNT_SEL { 9641 SC_SRPS_WINDOW_VALID = 0x00000000, 9642 SC_PSSW_WINDOW_VALID = 0x00000001, 9643 SC_TPQZ_WINDOW_VALID = 0x00000002, 9644 SC_QZQP_WINDOW_VALID = 0x00000003, 9645 SC_TRPK_WINDOW_VALID = 0x00000004, 9646 SC_SRPS_WINDOW_VALID_BUSY = 0x00000005, 9647 SC_PSSW_WINDOW_VALID_BUSY = 0x00000006, 9648 SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007, 9649 SC_QZQP_WINDOW_VALID_BUSY = 0x00000008, 9650 SC_TRPK_WINDOW_VALID_BUSY = 0x00000009, 9651 SC_STARVED_BY_PA = 0x0000000a, 9652 SC_STALLED_BY_PRIMFIFO = 0x0000000b, 9653 SC_STALLED_BY_DB_TILE = 0x0000000c, 9654 SC_STARVED_BY_DB_TILE = 0x0000000d, 9655 SC_STALLED_BY_TILEORDERFIFO = 0x0000000e, 9656 SC_STALLED_BY_TILEFIFO = 0x0000000f, 9657 SC_STALLED_BY_DB_QUAD = 0x00000010, 9658 SC_STARVED_BY_DB_QUAD = 0x00000011, 9659 SC_STALLED_BY_QUADFIFO = 0x00000012, 9660 SC_STALLED_BY_BCI = 0x00000013, 9661 SC_STALLED_BY_SPI = 0x00000014, 9662 SC_SCISSOR_DISCARD = 0x00000015, 9663 SC_BB_DISCARD = 0x00000016, 9664 SC_SUPERTILE_COUNT = 0x00000017, 9665 SC_SUPERTILE_PER_PRIM_H0 = 0x00000018, 9666 SC_SUPERTILE_PER_PRIM_H1 = 0x00000019, 9667 SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a, 9668 SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b, 9669 SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c, 9670 SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d, 9671 SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e, 9672 SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f, 9673 SC_SUPERTILE_PER_PRIM_H8 = 0x00000020, 9674 SC_SUPERTILE_PER_PRIM_H9 = 0x00000021, 9675 SC_SUPERTILE_PER_PRIM_H10 = 0x00000022, 9676 SC_SUPERTILE_PER_PRIM_H11 = 0x00000023, 9677 SC_SUPERTILE_PER_PRIM_H12 = 0x00000024, 9678 SC_SUPERTILE_PER_PRIM_H13 = 0x00000025, 9679 SC_SUPERTILE_PER_PRIM_H14 = 0x00000026, 9680 SC_SUPERTILE_PER_PRIM_H15 = 0x00000027, 9681 SC_SUPERTILE_PER_PRIM_H16 = 0x00000028, 9682 SC_TILE_PER_PRIM_H0 = 0x00000029, 9683 SC_TILE_PER_PRIM_H1 = 0x0000002a, 9684 SC_TILE_PER_PRIM_H2 = 0x0000002b, 9685 SC_TILE_PER_PRIM_H3 = 0x0000002c, 9686 SC_TILE_PER_PRIM_H4 = 0x0000002d, 9687 SC_TILE_PER_PRIM_H5 = 0x0000002e, 9688 SC_TILE_PER_PRIM_H6 = 0x0000002f, 9689 SC_TILE_PER_PRIM_H7 = 0x00000030, 9690 SC_TILE_PER_PRIM_H8 = 0x00000031, 9691 SC_TILE_PER_PRIM_H9 = 0x00000032, 9692 SC_TILE_PER_PRIM_H10 = 0x00000033, 9693 SC_TILE_PER_PRIM_H11 = 0x00000034, 9694 SC_TILE_PER_PRIM_H12 = 0x00000035, 9695 SC_TILE_PER_PRIM_H13 = 0x00000036, 9696 SC_TILE_PER_PRIM_H14 = 0x00000037, 9697 SC_TILE_PER_PRIM_H15 = 0x00000038, 9698 SC_TILE_PER_PRIM_H16 = 0x00000039, 9699 SC_TILE_PER_SUPERTILE_H0 = 0x0000003a, 9700 SC_TILE_PER_SUPERTILE_H1 = 0x0000003b, 9701 SC_TILE_PER_SUPERTILE_H2 = 0x0000003c, 9702 SC_TILE_PER_SUPERTILE_H3 = 0x0000003d, 9703 SC_TILE_PER_SUPERTILE_H4 = 0x0000003e, 9704 SC_TILE_PER_SUPERTILE_H5 = 0x0000003f, 9705 SC_TILE_PER_SUPERTILE_H6 = 0x00000040, 9706 SC_TILE_PER_SUPERTILE_H7 = 0x00000041, 9707 SC_TILE_PER_SUPERTILE_H8 = 0x00000042, 9708 SC_TILE_PER_SUPERTILE_H9 = 0x00000043, 9709 SC_TILE_PER_SUPERTILE_H10 = 0x00000044, 9710 SC_TILE_PER_SUPERTILE_H11 = 0x00000045, 9711 SC_TILE_PER_SUPERTILE_H12 = 0x00000046, 9712 SC_TILE_PER_SUPERTILE_H13 = 0x00000047, 9713 SC_TILE_PER_SUPERTILE_H14 = 0x00000048, 9714 SC_TILE_PER_SUPERTILE_H15 = 0x00000049, 9715 SC_TILE_PER_SUPERTILE_H16 = 0x0000004a, 9716 SC_TILE_PICKED_H1 = 0x0000004b, 9717 SC_TILE_PICKED_H2 = 0x0000004c, 9718 SC_TILE_PICKED_H3 = 0x0000004d, 9719 SC_TILE_PICKED_H4 = 0x0000004e, 9720 SC_QZ0_TILE_COUNT = 0x0000004f, 9721 SC_QZ1_TILE_COUNT = 0x00000050, 9722 SC_QZ2_TILE_COUNT = 0x00000051, 9723 SC_QZ3_TILE_COUNT = 0x00000052, 9724 SC_QZ0_TILE_COVERED_COUNT = 0x00000053, 9725 SC_QZ1_TILE_COVERED_COUNT = 0x00000054, 9726 SC_QZ2_TILE_COVERED_COUNT = 0x00000055, 9727 SC_QZ3_TILE_COVERED_COUNT = 0x00000056, 9728 SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00000057, 9729 SC_QZ1_TILE_NOT_COVERED_COUNT = 0x00000058, 9730 SC_QZ2_TILE_NOT_COVERED_COUNT = 0x00000059, 9731 SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005a, 9732 SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005b, 9733 SC_QZ0_QUAD_PER_TILE_H1 = 0x0000005c, 9734 SC_QZ0_QUAD_PER_TILE_H2 = 0x0000005d, 9735 SC_QZ0_QUAD_PER_TILE_H3 = 0x0000005e, 9736 SC_QZ0_QUAD_PER_TILE_H4 = 0x0000005f, 9737 SC_QZ0_QUAD_PER_TILE_H5 = 0x00000060, 9738 SC_QZ0_QUAD_PER_TILE_H6 = 0x00000061, 9739 SC_QZ0_QUAD_PER_TILE_H7 = 0x00000062, 9740 SC_QZ0_QUAD_PER_TILE_H8 = 0x00000063, 9741 SC_QZ0_QUAD_PER_TILE_H9 = 0x00000064, 9742 SC_QZ0_QUAD_PER_TILE_H10 = 0x00000065, 9743 SC_QZ0_QUAD_PER_TILE_H11 = 0x00000066, 9744 SC_QZ0_QUAD_PER_TILE_H12 = 0x00000067, 9745 SC_QZ0_QUAD_PER_TILE_H13 = 0x00000068, 9746 SC_QZ0_QUAD_PER_TILE_H14 = 0x00000069, 9747 SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006a, 9748 SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006b, 9749 SC_QZ1_QUAD_PER_TILE_H0 = 0x0000006c, 9750 SC_QZ1_QUAD_PER_TILE_H1 = 0x0000006d, 9751 SC_QZ1_QUAD_PER_TILE_H2 = 0x0000006e, 9752 SC_QZ1_QUAD_PER_TILE_H3 = 0x0000006f, 9753 SC_QZ1_QUAD_PER_TILE_H4 = 0x00000070, 9754 SC_QZ1_QUAD_PER_TILE_H5 = 0x00000071, 9755 SC_QZ1_QUAD_PER_TILE_H6 = 0x00000072, 9756 SC_QZ1_QUAD_PER_TILE_H7 = 0x00000073, 9757 SC_QZ1_QUAD_PER_TILE_H8 = 0x00000074, 9758 SC_QZ1_QUAD_PER_TILE_H9 = 0x00000075, 9759 SC_QZ1_QUAD_PER_TILE_H10 = 0x00000076, 9760 SC_QZ1_QUAD_PER_TILE_H11 = 0x00000077, 9761 SC_QZ1_QUAD_PER_TILE_H12 = 0x00000078, 9762 SC_QZ1_QUAD_PER_TILE_H13 = 0x00000079, 9763 SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007a, 9764 SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007b, 9765 SC_QZ1_QUAD_PER_TILE_H16 = 0x0000007c, 9766 SC_QZ2_QUAD_PER_TILE_H0 = 0x0000007d, 9767 SC_QZ2_QUAD_PER_TILE_H1 = 0x0000007e, 9768 SC_QZ2_QUAD_PER_TILE_H2 = 0x0000007f, 9769 SC_QZ2_QUAD_PER_TILE_H3 = 0x00000080, 9770 SC_QZ2_QUAD_PER_TILE_H4 = 0x00000081, 9771 SC_QZ2_QUAD_PER_TILE_H5 = 0x00000082, 9772 SC_QZ2_QUAD_PER_TILE_H6 = 0x00000083, 9773 SC_QZ2_QUAD_PER_TILE_H7 = 0x00000084, 9774 SC_QZ2_QUAD_PER_TILE_H8 = 0x00000085, 9775 SC_QZ2_QUAD_PER_TILE_H9 = 0x00000086, 9776 SC_QZ2_QUAD_PER_TILE_H10 = 0x00000087, 9777 SC_QZ2_QUAD_PER_TILE_H11 = 0x00000088, 9778 SC_QZ2_QUAD_PER_TILE_H12 = 0x00000089, 9779 SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008a, 9780 SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008b, 9781 SC_QZ2_QUAD_PER_TILE_H15 = 0x0000008c, 9782 SC_QZ2_QUAD_PER_TILE_H16 = 0x0000008d, 9783 SC_QZ3_QUAD_PER_TILE_H0 = 0x0000008e, 9784 SC_QZ3_QUAD_PER_TILE_H1 = 0x0000008f, 9785 SC_QZ3_QUAD_PER_TILE_H2 = 0x00000090, 9786 SC_QZ3_QUAD_PER_TILE_H3 = 0x00000091, 9787 SC_QZ3_QUAD_PER_TILE_H4 = 0x00000092, 9788 SC_QZ3_QUAD_PER_TILE_H5 = 0x00000093, 9789 SC_QZ3_QUAD_PER_TILE_H6 = 0x00000094, 9790 SC_QZ3_QUAD_PER_TILE_H7 = 0x00000095, 9791 SC_QZ3_QUAD_PER_TILE_H8 = 0x00000096, 9792 SC_QZ3_QUAD_PER_TILE_H9 = 0x00000097, 9793 SC_QZ3_QUAD_PER_TILE_H10 = 0x00000098, 9794 SC_QZ3_QUAD_PER_TILE_H11 = 0x00000099, 9795 SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009a, 9796 SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009b, 9797 SC_QZ3_QUAD_PER_TILE_H14 = 0x0000009c, 9798 SC_QZ3_QUAD_PER_TILE_H15 = 0x0000009d, 9799 SC_QZ3_QUAD_PER_TILE_H16 = 0x0000009e, 9800 SC_QZ0_QUAD_COUNT = 0x0000009f, 9801 SC_QZ1_QUAD_COUNT = 0x000000a0, 9802 SC_QZ2_QUAD_COUNT = 0x000000a1, 9803 SC_QZ3_QUAD_COUNT = 0x000000a2, 9804 SC_P0_HIZ_TILE_COUNT = 0x000000a3, 9805 SC_P1_HIZ_TILE_COUNT = 0x000000a4, 9806 SC_P2_HIZ_TILE_COUNT = 0x000000a5, 9807 SC_P3_HIZ_TILE_COUNT = 0x000000a6, 9808 SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000a7, 9809 SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000a8, 9810 SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000a9, 9811 SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000aa, 9812 SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000ab, 9813 SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000ac, 9814 SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000ad, 9815 SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000ae, 9816 SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000af, 9817 SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b0, 9818 SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b1, 9819 SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b2, 9820 SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b3, 9821 SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b4, 9822 SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b5, 9823 SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000b6, 9824 SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000b7, 9825 SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000b8, 9826 SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000b9, 9827 SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000ba, 9828 SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bb, 9829 SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000bc, 9830 SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000bd, 9831 SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000be, 9832 SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000bf, 9833 SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c0, 9834 SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c1, 9835 SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c2, 9836 SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c3, 9837 SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c4, 9838 SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c5, 9839 SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000c6, 9840 SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000c7, 9841 SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000c8, 9842 SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000c9, 9843 SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ca, 9844 SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cb, 9845 SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000cc, 9846 SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000cd, 9847 SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000ce, 9848 SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000cf, 9849 SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d0, 9850 SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d1, 9851 SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d2, 9852 SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d3, 9853 SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d4, 9854 SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d5, 9855 SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000d6, 9856 SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000d7, 9857 SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000d8, 9858 SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000d9, 9859 SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000da, 9860 SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000db, 9861 SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000dc, 9862 SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000dd, 9863 SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000de, 9864 SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000df, 9865 SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e0, 9866 SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e1, 9867 SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e2, 9868 SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e3, 9869 SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e4, 9870 SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e5, 9871 SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000e6, 9872 SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000e7, 9873 SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000e8, 9874 SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000e9, 9875 SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ea, 9876 SC_P0_HIZ_QUAD_COUNT = 0x000000eb, 9877 SC_P1_HIZ_QUAD_COUNT = 0x000000ec, 9878 SC_P2_HIZ_QUAD_COUNT = 0x000000ed, 9879 SC_P3_HIZ_QUAD_COUNT = 0x000000ee, 9880 SC_P0_DETAIL_QUAD_COUNT = 0x000000ef, 9881 SC_P1_DETAIL_QUAD_COUNT = 0x000000f0, 9882 SC_P2_DETAIL_QUAD_COUNT = 0x000000f1, 9883 SC_P3_DETAIL_QUAD_COUNT = 0x000000f2, 9884 SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f3, 9885 SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f4, 9886 SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f5, 9887 SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000f6, 9888 SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000f7, 9889 SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000f8, 9890 SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000f9, 9891 SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fa, 9892 SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000fb, 9893 SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x000000fc, 9894 SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x000000fd, 9895 SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x000000fe, 9896 SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x000000ff, 9897 SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000100, 9898 SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000101, 9899 SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000102, 9900 SC_EARLYZ_QUAD_COUNT = 0x00000103, 9901 SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000104, 9902 SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000105, 9903 SC_EARLYZ_QUAD_WITH_3_PIX = 0x00000106, 9904 SC_EARLYZ_QUAD_WITH_4_PIX = 0x00000107, 9905 SC_PKR_QUAD_PER_ROW_H1 = 0x00000108, 9906 SC_PKR_QUAD_PER_ROW_H2 = 0x00000109, 9907 SC_PKR_4X2_QUAD_SPLIT = 0x0000010a, 9908 SC_PKR_4X2_FILL_QUAD = 0x0000010b, 9909 SC_PKR_END_OF_VECTOR = 0x0000010c, 9910 SC_PKR_CONTROL_XFER = 0x0000010d, 9911 SC_PKR_DBHANG_FORCE_EOV = 0x0000010e, 9912 SC_REG_SCLK_BUSY = 0x0000010f, 9913 SC_GRP0_DYN_SCLK_BUSY = 0x00000110, 9914 SC_GRP1_DYN_SCLK_BUSY = 0x00000111, 9915 SC_GRP2_DYN_SCLK_BUSY = 0x00000112, 9916 SC_GRP3_DYN_SCLK_BUSY = 0x00000113, 9917 SC_GRP4_DYN_SCLK_BUSY = 0x00000114, 9918 SC_PA0_SC_DATA_FIFO_RD = 0x00000115, 9919 SC_PA0_SC_DATA_FIFO_WE = 0x00000116, 9920 SC_PA1_SC_DATA_FIFO_RD = 0x00000117, 9921 SC_PA1_SC_DATA_FIFO_WE = 0x00000118, 9922 SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000119, 9923 SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011a, 9924 SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011b, 9925 SC_PS_ARB_STALLED_FROM_BELOW = 0x0000011c, 9926 SC_PS_ARB_STARVED_FROM_ABOVE = 0x0000011d, 9927 SC_PS_ARB_SC_BUSY = 0x0000011e, 9928 SC_PS_ARB_PA_SC_BUSY = 0x0000011f, 9929 SC_PA2_SC_DATA_FIFO_RD = 0x00000120, 9930 SC_PA2_SC_DATA_FIFO_WE = 0x00000121, 9931 SC_PA3_SC_DATA_FIFO_RD = 0x00000122, 9932 SC_PA3_SC_DATA_FIFO_WE = 0x00000123, 9933 SC_PA_SC_DEALLOC_0_0_WE = 0x00000124, 9934 SC_PA_SC_DEALLOC_0_1_WE = 0x00000125, 9935 SC_PA_SC_DEALLOC_1_0_WE = 0x00000126, 9936 SC_PA_SC_DEALLOC_1_1_WE = 0x00000127, 9937 SC_PA_SC_DEALLOC_2_0_WE = 0x00000128, 9938 SC_PA_SC_DEALLOC_2_1_WE = 0x00000129, 9939 SC_PA_SC_DEALLOC_3_0_WE = 0x0000012a, 9940 SC_PA_SC_DEALLOC_3_1_WE = 0x0000012b, 9941 SC_PA0_SC_EOP_WE = 0x0000012c, 9942 SC_PA0_SC_EOPG_WE = 0x0000012d, 9943 SC_PA0_SC_EVENT_WE = 0x0000012e, 9944 SC_PA1_SC_EOP_WE = 0x0000012f, 9945 SC_PA1_SC_EOPG_WE = 0x00000130, 9946 SC_PA1_SC_EVENT_WE = 0x00000131, 9947 SC_PA2_SC_EOP_WE = 0x00000132, 9948 SC_PA2_SC_EOPG_WE = 0x00000133, 9949 SC_PA2_SC_EVENT_WE = 0x00000134, 9950 SC_PA3_SC_EOP_WE = 0x00000135, 9951 SC_PA3_SC_EOPG_WE = 0x00000136, 9952 SC_PA3_SC_EVENT_WE = 0x00000137, 9953 SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x00000138, 9954 SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x00000139, 9955 SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013a, 9956 SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013b, 9957 SC_PS_ARB_EVENT_SYNC_POP = 0x0000013c, 9958 SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x0000013d, 9959 SC_PA0_SC_FPOV_WE = 0x0000013e, 9960 SC_PA1_SC_FPOV_WE = 0x0000013f, 9961 SC_PA2_SC_FPOV_WE = 0x00000140, 9962 SC_PA3_SC_FPOV_WE = 0x00000141, 9963 SC_PA0_SC_LPOV_WE = 0x00000142, 9964 SC_PA1_SC_LPOV_WE = 0x00000143, 9965 SC_PA2_SC_LPOV_WE = 0x00000144, 9966 SC_PA3_SC_LPOV_WE = 0x00000145, 9967 SC_SC_SPI_DEALLOC_0_0 = 0x00000146, 9968 SC_SC_SPI_DEALLOC_0_1 = 0x00000147, 9969 SC_SC_SPI_DEALLOC_0_2 = 0x00000148, 9970 SC_SC_SPI_DEALLOC_1_0 = 0x00000149, 9971 SC_SC_SPI_DEALLOC_1_1 = 0x0000014a, 9972 SC_SC_SPI_DEALLOC_1_2 = 0x0000014b, 9973 SC_SC_SPI_DEALLOC_2_0 = 0x0000014c, 9974 SC_SC_SPI_DEALLOC_2_1 = 0x0000014d, 9975 SC_SC_SPI_DEALLOC_2_2 = 0x0000014e, 9976 SC_SC_SPI_DEALLOC_3_0 = 0x0000014f, 9977 SC_SC_SPI_DEALLOC_3_1 = 0x00000150, 9978 SC_SC_SPI_DEALLOC_3_2 = 0x00000151, 9979 SC_SC_SPI_FPOV_0 = 0x00000152, 9980 SC_SC_SPI_FPOV_1 = 0x00000153, 9981 SC_SC_SPI_FPOV_2 = 0x00000154, 9982 SC_SC_SPI_FPOV_3 = 0x00000155, 9983 SC_SC_SPI_EVENT = 0x00000156, 9984 SC_PS_TS_EVENT_FIFO_PUSH = 0x00000157, 9985 SC_PS_TS_EVENT_FIFO_POP = 0x00000158, 9986 SC_PS_CTX_DONE_FIFO_PUSH = 0x00000159, 9987 SC_PS_CTX_DONE_FIFO_POP = 0x0000015a, 9988 SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015b, 9989 SC_EOP_SYNC_WINDOW = 0x0000015c, 9990 SC_PA0_SC_NULL_WE = 0x0000015d, 9991 SC_PA0_SC_NULL_DEALLOC_WE = 0x0000015e, 9992 SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x0000015f, 9993 SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000160, 9994 SC_PA0_SC_DEALLOC_0_RD = 0x00000161, 9995 SC_PA0_SC_DEALLOC_1_RD = 0x00000162, 9996 SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000163, 9997 SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000164, 9998 SC_PA1_SC_DEALLOC_0_RD = 0x00000165, 9999 SC_PA1_SC_DEALLOC_1_RD = 0x00000166, 10000 SC_PA1_SC_NULL_WE = 0x00000167, 10001 SC_PA1_SC_NULL_DEALLOC_WE = 0x00000168, 10002 SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x00000169, 10003 SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016a, 10004 SC_PA2_SC_DEALLOC_0_RD = 0x0000016b, 10005 SC_PA2_SC_DEALLOC_1_RD = 0x0000016c, 10006 SC_PA2_SC_NULL_WE = 0x0000016d, 10007 SC_PA2_SC_NULL_DEALLOC_WE = 0x0000016e, 10008 SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x0000016f, 10009 SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000170, 10010 SC_PA3_SC_DEALLOC_0_RD = 0x00000171, 10011 SC_PA3_SC_DEALLOC_1_RD = 0x00000172, 10012 SC_PA3_SC_NULL_WE = 0x00000173, 10013 SC_PA3_SC_NULL_DEALLOC_WE = 0x00000174, 10014 SC_PS_PA0_SC_FIFO_EMPTY = 0x00000175, 10015 SC_PS_PA0_SC_FIFO_FULL = 0x00000176, 10016 SC_PA0_PS_DATA_SEND = 0x00000177, 10017 SC_PS_PA1_SC_FIFO_EMPTY = 0x00000178, 10018 SC_PS_PA1_SC_FIFO_FULL = 0x00000179, 10019 SC_PA1_PS_DATA_SEND = 0x0000017a, 10020 SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017b, 10021 SC_PS_PA2_SC_FIFO_FULL = 0x0000017c, 10022 SC_PA2_PS_DATA_SEND = 0x0000017d, 10023 SC_PS_PA3_SC_FIFO_EMPTY = 0x0000017e, 10024 SC_PS_PA3_SC_FIFO_FULL = 0x0000017f, 10025 SC_PA3_PS_DATA_SEND = 0x00000180, 10026 SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000181, 10027 SC_BUSY_CNT_NOT_ZERO = 0x00000182, 10028 SC_BM_BUSY = 0x00000183, 10029 SC_BACKEND_BUSY = 0x00000184, 10030 SC_SCF_SCB_INTERFACE_BUSY = 0x00000185, 10031 SC_SCB_BUSY = 0x00000186, 10032 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187, 10033 SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188, 10034 SC_PBB_BIN_HIST_NUM_PRIMS = 0x00000189, 10035 SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018a, 10036 SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018b, 10037 SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x0000018c, 10038 SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x0000018d, 10039 SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x0000018e, 10040 SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x0000018f, 10041 SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190, 10042 SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000191, 10043 SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000192, 10044 SC_PBB_BUSY = 0x00000193, 10045 SC_PBB_BUSY_AND_RTR = 0x00000194, 10046 SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000195, 10047 SC_PBB_NUM_BINS = 0x00000196, 10048 SC_PBB_END_OF_BIN = 0x00000197, 10049 SC_PBB_END_OF_BATCH = 0x00000198, 10050 SC_PBB_PRIMBIN_PROCESSED = 0x00000199, 10051 SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019a, 10052 SC_PBB_NONBINNED_PRIM = 0x0000019b, 10053 SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x0000019c, 10054 SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x0000019d, 10055 SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e, 10056 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f, 10057 SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0, 10058 SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1, 10059 SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a2, 10060 SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a3, 10061 SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a4, 10062 SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a5, 10063 SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001a6, 10064 SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001a7, 10065 SC_POPS_FORCE_EOV = 0x000001a8, 10066 SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE = 0x000001a9, 10067 SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE = 0x000001aa, 10068 } SC_PERFCNT_SEL; 10069 10070 /* 10071 * SePairXsel enum 10072 */ 10073 10074 typedef enum SePairXsel { 10075 RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000, 10076 RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001, 10077 RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002, 10078 RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003, 10079 RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 0x00000004, 10080 } SePairXsel; 10081 10082 /* 10083 * SePairYsel enum 10084 */ 10085 10086 typedef enum SePairYsel { 10087 RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000, 10088 RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001, 10089 RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002, 10090 RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003, 10091 RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 0x00000004, 10092 } SePairYsel; 10093 10094 /* 10095 * SePairMap enum 10096 */ 10097 10098 typedef enum SePairMap { 10099 RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000, 10100 RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001, 10101 RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002, 10102 RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003, 10103 } SePairMap; 10104 10105 /* 10106 * SeXsel enum 10107 */ 10108 10109 typedef enum SeXsel { 10110 RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000, 10111 RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001, 10112 RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002, 10113 RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003, 10114 RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 0x00000004, 10115 } SeXsel; 10116 10117 /* 10118 * SeYsel enum 10119 */ 10120 10121 typedef enum SeYsel { 10122 RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000, 10123 RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001, 10124 RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002, 10125 RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003, 10126 RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 0x00000004, 10127 } SeYsel; 10128 10129 /* 10130 * SeMap enum 10131 */ 10132 10133 typedef enum SeMap { 10134 RASTER_CONFIG_SE_MAP_0 = 0x00000000, 10135 RASTER_CONFIG_SE_MAP_1 = 0x00000001, 10136 RASTER_CONFIG_SE_MAP_2 = 0x00000002, 10137 RASTER_CONFIG_SE_MAP_3 = 0x00000003, 10138 } SeMap; 10139 10140 /* 10141 * ScXsel enum 10142 */ 10143 10144 typedef enum ScXsel { 10145 RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000, 10146 RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001, 10147 RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002, 10148 RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003, 10149 } ScXsel; 10150 10151 /* 10152 * ScYsel enum 10153 */ 10154 10155 typedef enum ScYsel { 10156 RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000, 10157 RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001, 10158 RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002, 10159 RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003, 10160 } ScYsel; 10161 10162 /* 10163 * ScMap enum 10164 */ 10165 10166 typedef enum ScMap { 10167 RASTER_CONFIG_SC_MAP_0 = 0x00000000, 10168 RASTER_CONFIG_SC_MAP_1 = 0x00000001, 10169 RASTER_CONFIG_SC_MAP_2 = 0x00000002, 10170 RASTER_CONFIG_SC_MAP_3 = 0x00000003, 10171 } ScMap; 10172 10173 /* 10174 * PkrXsel2 enum 10175 */ 10176 10177 typedef enum PkrXsel2 { 10178 RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000, 10179 RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001, 10180 RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002, 10181 RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003, 10182 } PkrXsel2; 10183 10184 /* 10185 * PkrXsel enum 10186 */ 10187 10188 typedef enum PkrXsel { 10189 RASTER_CONFIG_PKR_XSEL_0 = 0x00000000, 10190 RASTER_CONFIG_PKR_XSEL_1 = 0x00000001, 10191 RASTER_CONFIG_PKR_XSEL_2 = 0x00000002, 10192 RASTER_CONFIG_PKR_XSEL_3 = 0x00000003, 10193 } PkrXsel; 10194 10195 /* 10196 * PkrYsel enum 10197 */ 10198 10199 typedef enum PkrYsel { 10200 RASTER_CONFIG_PKR_YSEL_0 = 0x00000000, 10201 RASTER_CONFIG_PKR_YSEL_1 = 0x00000001, 10202 RASTER_CONFIG_PKR_YSEL_2 = 0x00000002, 10203 RASTER_CONFIG_PKR_YSEL_3 = 0x00000003, 10204 } PkrYsel; 10205 10206 /* 10207 * PkrMap enum 10208 */ 10209 10210 typedef enum PkrMap { 10211 RASTER_CONFIG_PKR_MAP_0 = 0x00000000, 10212 RASTER_CONFIG_PKR_MAP_1 = 0x00000001, 10213 RASTER_CONFIG_PKR_MAP_2 = 0x00000002, 10214 RASTER_CONFIG_PKR_MAP_3 = 0x00000003, 10215 } PkrMap; 10216 10217 /* 10218 * RbXsel enum 10219 */ 10220 10221 typedef enum RbXsel { 10222 RASTER_CONFIG_RB_XSEL_0 = 0x00000000, 10223 RASTER_CONFIG_RB_XSEL_1 = 0x00000001, 10224 } RbXsel; 10225 10226 /* 10227 * RbYsel enum 10228 */ 10229 10230 typedef enum RbYsel { 10231 RASTER_CONFIG_RB_YSEL_0 = 0x00000000, 10232 RASTER_CONFIG_RB_YSEL_1 = 0x00000001, 10233 } RbYsel; 10234 10235 /* 10236 * RbXsel2 enum 10237 */ 10238 10239 typedef enum RbXsel2 { 10240 RASTER_CONFIG_RB_XSEL2_0 = 0x00000000, 10241 RASTER_CONFIG_RB_XSEL2_1 = 0x00000001, 10242 RASTER_CONFIG_RB_XSEL2_2 = 0x00000002, 10243 RASTER_CONFIG_RB_XSEL2_3 = 0x00000003, 10244 } RbXsel2; 10245 10246 /* 10247 * RbMap enum 10248 */ 10249 10250 typedef enum RbMap { 10251 RASTER_CONFIG_RB_MAP_0 = 0x00000000, 10252 RASTER_CONFIG_RB_MAP_1 = 0x00000001, 10253 RASTER_CONFIG_RB_MAP_2 = 0x00000002, 10254 RASTER_CONFIG_RB_MAP_3 = 0x00000003, 10255 } RbMap; 10256 10257 /* 10258 * BinningMode enum 10259 */ 10260 10261 typedef enum BinningMode { 10262 BINNING_ALLOWED = 0x00000000, 10263 FORCE_BINNING_ON = 0x00000001, 10264 DISABLE_BINNING_USE_NEW_SC = 0x00000002, 10265 DISABLE_BINNING_USE_LEGACY_SC = 0x00000003, 10266 } BinningMode; 10267 10268 /* 10269 * BinEventCntl enum 10270 */ 10271 10272 typedef enum BinEventCntl { 10273 BINNER_BREAK_BATCH = 0x00000000, 10274 BINNER_PIPELINE = 0x00000001, 10275 BINNER_DROP_ASSERT = 0x00000002, 10276 } BinEventCntl; 10277 10278 /* 10279 * CovToShaderSel enum 10280 */ 10281 10282 typedef enum CovToShaderSel { 10283 INPUT_COVERAGE = 0x00000000, 10284 INPUT_INNER_COVERAGE = 0x00000001, 10285 INPUT_DEPTH_COVERAGE = 0x00000002, 10286 RAW = 0x00000003, 10287 } CovToShaderSel; 10288 10289 /******************************************************* 10290 * RMI Enums 10291 *******************************************************/ 10292 10293 /* 10294 * RMIPerfSel enum 10295 */ 10296 10297 typedef enum RMIPerfSel { 10298 RMI_PERF_SEL_NONE = 0x00000000, 10299 RMI_PERF_SEL_BUSY = 0x00000001, 10300 RMI_PERF_SEL_REG_CLK_VLD = 0x00000002, 10301 RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003, 10302 RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004, 10303 RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005, 10304 RMI_PERF_SEL_PERF_WINDOW = 0x00000006, 10305 RMI_PERF_SEL_EVENT_SEND = 0x00000007, 10306 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008, 10307 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009, 10308 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a, 10309 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b, 10310 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c, 10311 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d, 10312 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e, 10313 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f, 10314 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010, 10315 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011, 10316 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012, 10317 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013, 10318 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014, 10319 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015, 10320 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016, 10321 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017, 10322 RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018, 10323 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019, 10324 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a, 10325 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b, 10326 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c, 10327 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d, 10328 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e, 10329 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f, 10330 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020, 10331 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021, 10332 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022, 10333 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023, 10334 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024, 10335 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025, 10336 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026, 10337 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027, 10338 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028, 10339 RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029, 10340 RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x0000002a, 10341 RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 0x0000002b, 10342 RMI_PERF_SEL_UTCL1_REQUEST = 0x0000002c, 10343 RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x0000002d, 10344 RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x0000002e, 10345 RMI_PERF_SEL_UTCL1_LFIFO_FULL = 0x0000002f, 10346 RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x00000030, 10347 RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000031, 10348 RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x00000032, 10349 RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 0x00000033, 10350 RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 0x00000034, 10351 RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000035, 10352 RMI_PERF_SEL_RB_RMI_WRREQ_BUSY = 0x00000036, 10353 RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x00000037, 10354 RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x00000038, 10355 RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x00000039, 10356 RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000003a, 10357 RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000003b, 10358 RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000003c, 10359 RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x0000003d, 10360 RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x0000003e, 10361 RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 0x0000003f, 10362 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000040, 10363 RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000041, 10364 RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000042, 10365 RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000043, 10366 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000044, 10367 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000045, 10368 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000046, 10369 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x00000047, 10370 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x00000048, 10371 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x00000049, 10372 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000004a, 10373 RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000004b, 10374 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000004c, 10375 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x0000004d, 10376 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x0000004e, 10377 RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x0000004f, 10378 RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000050, 10379 RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000051, 10380 RMI_PERF_SEL_RB_RMI_RDREQ_BUSY = 0x00000052, 10381 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000053, 10382 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000054, 10383 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000055, 10384 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000056, 10385 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x00000057, 10386 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x00000058, 10387 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x00000059, 10388 RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000005a, 10389 RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000005b, 10390 RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000005c, 10391 RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x0000005d, 10392 RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x0000005e, 10393 RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x0000005f, 10394 RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000060, 10395 RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000061, 10396 RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000062, 10397 RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000063, 10398 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000064, 10399 RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000065, 10400 RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000066, 10401 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000067, 10402 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x00000068, 10403 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x00000069, 10404 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000006a, 10405 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000006b, 10406 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000006c, 10407 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x0000006d, 10408 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x0000006e, 10409 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x0000006f, 10410 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000070, 10411 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000071, 10412 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000072, 10413 RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000073, 10414 RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000074, 10415 RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000075, 10416 RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000076, 10417 RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x00000077, 10418 RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x00000078, 10419 RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x00000079, 10420 RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000007a, 10421 RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000007b, 10422 RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000007c, 10423 RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x0000007d, 10424 RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000007e, 10425 RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x0000007f, 10426 RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000080, 10427 RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000081, 10428 RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000082, 10429 RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000083, 10430 RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000084, 10431 RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000085, 10432 RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000086, 10433 RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x00000087, 10434 RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x00000088, 10435 RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000089, 10436 RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x0000008a, 10437 RMI_PERF_SEL_UTCL1_BUSY = 0x0000008b, 10438 RMI_PERF_SEL_RMI_UTC_REQ = 0x0000008c, 10439 RMI_PERF_SEL_RMI_UTC_BUSY = 0x0000008d, 10440 RMI_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000008e, 10441 RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 0x0000008f, 10442 RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 0x00000090, 10443 RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 0x00000091, 10444 RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS = 0x00000092, 10445 RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x00000093, 10446 RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 0x00000094, 10447 RMI_PERF_SEL_LAT_FIFO_NUM_USED = 0x00000095, 10448 RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 0x00000096, 10449 RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 0x00000097, 10450 RMI_PERF_SEL_XNACK_FIFO_FULL = 0x00000098, 10451 RMI_PERF_SEL_XNACK_FIFO_BUSY = 0x00000099, 10452 RMI_PERF_SEL_LAT_FIFO_FULL = 0x0000009a, 10453 RMI_PERF_SEL_SKID_FIFO_DEPTH = 0x0000009b, 10454 RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x0000009c, 10455 RMI_PERF_SEL_PRT_FIFO_NUM_USED = 0x0000009d, 10456 RMI_PERF_SEL_PRT_FIFO_REQ = 0x0000009e, 10457 RMI_PERF_SEL_PRT_FIFO_BUSY = 0x0000009f, 10458 RMI_PERF_SEL_TCIW_REQ = 0x000000a0, 10459 RMI_PERF_SEL_TCIW_BUSY = 0x000000a1, 10460 RMI_PERF_SEL_SKID_FIFO_REQ = 0x000000a2, 10461 RMI_PERF_SEL_SKID_FIFO_BUSY = 0x000000a3, 10462 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 0x000000a4, 10463 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 0x000000a5, 10464 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 0x000000a6, 10465 RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 0x000000a7, 10466 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 0x000000a8, 10467 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 0x000000a9, 10468 RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 0x000000aa, 10469 RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 0x000000ab, 10470 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000ac, 10471 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000ad, 10472 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000ae, 10473 RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000af, 10474 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000b0, 10475 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000b1, 10476 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000b2, 10477 RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000b3, 10478 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000b4, 10479 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000b5, 10480 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000b6, 10481 RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000b7, 10482 RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 0x000000b8, 10483 RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 0x000000b9, 10484 RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 0x000000ba, 10485 RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 0x000000bb, 10486 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 0x000000bc, 10487 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 0x000000bd, 10488 RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 0x000000be, 10489 RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 0x000000bf, 10490 RMI_PERF_SEL_UTC_POP_RTS_RTR = 0x000000c0, 10491 RMI_PERF_SEL_UTC_POP_RTSB_RTR = 0x000000c1, 10492 RMI_PERF_SEL_UTC_POP_RTS_RTRB = 0x000000c2, 10493 RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 0x000000c3, 10494 RMI_PERF_SEL_POP_XNACK_RTS_RTR = 0x000000c4, 10495 RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 0x000000c5, 10496 RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 0x000000c6, 10497 RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 0x000000c7, 10498 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 0x000000c8, 10499 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 0x000000c9, 10500 RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 0x000000ca, 10501 RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 0x000000cb, 10502 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000cc, 10503 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000cd, 10504 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000ce, 10505 RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000cf, 10506 RMI_PERF_SEL_SKID_FIFO_IN_RTS = 0x000000d0, 10507 RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 0x000000d1, 10508 RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 0x000000d2, 10509 RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 0x000000d3, 10510 RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 0x000000d4, 10511 RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000d5, 10512 RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 0x000000d6, 10513 RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 0x000000d7, 10514 RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 0x000000d8, 10515 RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 0x000000d9, 10516 RMI_PERF_SEL_REORDER_FIFO_REQ = 0x000000da, 10517 RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x000000db, 10518 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x000000dc, 10519 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x000000dd, 10520 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x000000de, 10521 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x000000df, 10522 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x000000e0, 10523 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x000000e1, 10524 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x000000e2, 10525 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x000000e3, 10526 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x000000e4, 10527 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 0x000000e5, 10528 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 0x000000e6, 10529 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 0x000000e7, 10530 RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 0x000000e8, 10531 } RMIPerfSel; 10532 10533 10534 #endif /*_vega10_ENUM_HEADER*/ 10535 10536