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Searched refs:SHADER_OPCODE_URB_WRITE_SIMD8_MASKED (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_shader.cpp320 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: in brw_instruction_name()
981 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: in has_side_effects()
Dbrw_eu_defines.h431 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED, enumerator
Dbrw_fs_generator.cpp600 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED || in generate_urb_write()
2010 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: in generate_code()
Dbrw_fs.cpp267 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: in is_send_from_grf()
809 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: in size_read()
1396 prev->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED || in emit_gs_thread_end()
5164 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED: in get_lowered_simd_width()
6291 fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED, in run_tcs_single_patch()
Dbrw_fs_nir.cpp1872 opcode = SHADER_OPCODE_URB_WRITE_SIMD8_MASKED; in emit_gs_control_data_bits()
2751 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED; in nir_emit_tcs_intrinsic()
2775 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED; in nir_emit_tcs_intrinsic()