| /external/v8/src/mips/ |
| D | constants-mips.h | 503 SLLV = ((0U << 3) + 4), enumerator
1284 FunctionFieldToBitNumber(SLLV) | FunctionFieldToBitNumber(SRLV) |
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| D | disasm-mips.cc | 1316 case SLLV: in DecodeTypeRegisterSPECIAL()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1023 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) in EmitAtomicBinaryPartword()
1026 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); in EmitAtomicBinaryPartword()
1251 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) in EmitAtomicCmpSwapPartword()
1256 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) in EmitAtomicCmpSwapPartword()
1260 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) in EmitAtomicCmpSwapPartword()
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 485 SLLV = ((0U << 3) + 4), enumerator
1324 FunctionFieldToBitNumber(SLLV) | FunctionFieldToBitNumber(DSLLV) |
|
| D | disasm-mips64.cc | 1487 case SLLV: in DecodeTypeRegisterSPECIAL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 124 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 158 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 226 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 222 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1669 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicBinaryPartword()
1672 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1852 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicCmpSwapPartword()
1857 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) in emitAtomicCmpSwapPartword()
1861 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) in emitAtomicCmpSwapPartword()
|
| D | MipsScheduleP5600.td | 213 ADDu, SLLV, SRAV, SRLV, LSA, COPY)>;
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| D | MipsInstrInfo.td | 2082 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
2780 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
2786 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1321 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicBinaryPartword()
1324 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1584 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicCmpSwapPartword()
1589 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) in emitAtomicCmpSwapPartword()
1593 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) in emitAtomicCmpSwapPartword()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_32.c | 397 EMIT_SHIFT(SLL, SLLV); in emit_single_op()
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| D | sljitNativeMIPS_64.c | 491 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV); in emit_single_op()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r3/ |
| D | valid.s | 271 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 271 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 272 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 305 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 345 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 339 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 287 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 286 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 349 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 766 {DBGFIELD("SLLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #491
1786 {DBGFIELD("SLLV") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #491
2691 case 491: // SLLV
|