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Searched refs:SPRN_L1CSR2 (Results 1 – 1 of 1) sorted by relevance

/external/u-boot/arch/powerpc/include/asm/
Dprocessor.h497 #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ macro
735 #define L1CSR2 SPRN_L1CSR2