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Searched refs:SRC0 (Results 1 – 12 of 12) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.exp.compr.ll18 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
20 ; GCN: exp mrt0 [[SRC0]], [[SRC0]], off, off done compr{{$}}
27 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
36 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
38 ; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}}
45 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
47 ; GCN: exp mrt0 off, [[SRC0]], off, off done compr{{$}}
54 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
56 ; GCN: exp mrt0 off, [[SRC0]], off, [[SRC1]] done compr{{$}}
73 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00
[all …]
Dllvm.amdgcn.exp.ll20 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
24 ; GCN: exp mrt0 [[SRC0]], off, off, off done{{$}}
31 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
42 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
53 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
64 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
68 ; GCN: exp mrt0 [[SRC0]], [[SRC1]], off, off done{{$}}
75 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
79 ; GCN: exp mrt0 [[SRC0]], off, [[SRC2]], off done{{$}}
86 ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
[all …]
Dsminmax.ll77 ; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
80 ; GFX9-DAG: v_sub_u32_e32 [[NEG0:v[0-9]+]], 0, [[SRC0:v[0-9]+]]
83 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]]
143 ; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
148 ; GFX9-DAG: v_sub_u32_e32 [[NEG0:v[0-9]+]], 0, [[SRC0:v[0-9]+]]
153 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]]
Dmul.ll111 ; GCN: s_load_dword [[SRC0:s[0-9]+]],
113 ; GCN: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
/external/mesa3d/src/mesa/x86/
Dx86_xform3.S41 #define SRC0 REGOFF(0, ESI) macro
100 FLD_S( SRC0 ) /* F4 */
102 FLD_S( SRC0 ) /* F5 F4 */
104 FLD_S( SRC0 ) /* F6 F5 F4 */
106 FLD_S( SRC0 ) /* F7 F6 F5 F4 */
208 FLD_S( SRC0 ) /* F4 */
288 FLD_S( SRC0 ) /* F4 */
290 FLD_S( SRC0 ) /* F5 F4 */
292 FLD_S( SRC0 ) /* F6 F5 F4 */
383 FLD_S( SRC0 ) /* F4 */
[all …]
Dx86_xform2.S41 #define SRC0 REGOFF(0, ESI) macro
100 FLD_S( SRC0 ) /* F4 */
102 FLD_S( SRC0 ) /* F5 F4 */
104 FLD_S( SRC0 ) /* F6 F5 F4 */
106 FLD_S( SRC0 ) /* F7 F6 F5 F4 */
194 FLD_S( SRC0 ) /* F4 */
257 FLD_S( SRC0 ) /* F4 */
259 FLD_S( SRC0 ) /* F5 F4 */
261 FLD_S( SRC0 ) /* F6 F5 F4 */
342 FLD_S( SRC0 ) /* F4 */
[all …]
Dx86_xform4.S41 #define SRC0 REGOFF(0, ESI) macro
100 FLD_S( SRC0 ) /* F4 */
102 FLD_S( SRC0 ) /* F5 F4 */
104 FLD_S( SRC0 ) /* F6 F5 F4 */
106 FLD_S( SRC0 ) /* F7 F6 F5 F4 */
215 FLD_S( SRC0 ) /* F4 */
298 FLD_S( SRC0 ) /* F4 */
300 FLD_S( SRC0 ) /* F5 F4 */
302 FLD_S( SRC0 ) /* F6 F5 F4 */
401 FLD_S( SRC0 ) /* F4 */
[all …]
Dx86_cliptest.S36 #define SRC0 REGOFF(0, ESI) macro
189 MOV_L( SRC0, EBX )
227 FLD_S( SRC0 ) /* F0 F3 */
355 MOV_L( SRC0, EBX )
/external/llvm/test/CodeGen/AMDGPU/
Dsminmax.ll57 ; GCN-DAG: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
60 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]]
116 ; GCN-DAG: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
121 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]]
Dmul.ll111 ; SI: s_load_dword [[SRC0:s[0-9]+]],
113 ; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
/external/webp/src/dsp/
Drescaler_neon.c32 #define STORE_32x8(SRC0, SRC1, DST) do { \ argument
33 vst1q_u32((DST) + 0, SRC0); \
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/
Dx86-avx512.ll936 ; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[SRC0:%.*]], float [[TMP6]], i64 0
951 ; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> [[SRC0:%.*]], float [[TMP6]], i64 0
966 ; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[SRC0:%.*]], double [[TMP6]], i64 0
981 ; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[SRC0:%.*]], double [[TMP6]], i64 0