/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | llvm.amdgcn.exp.ll | 22 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 33 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 44 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 46 ; GCN: exp mrt0 off, off, [[SRC2]], off done{{$}} 55 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 66 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 77 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 79 ; GCN: exp mrt0 [[SRC0]], off, [[SRC2]], off done{{$}} 88 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 101 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 [all …]
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D | combine-ftrunc.ll | 27 ; GCN: s_load_dwordx2 s{{\[}}[[SRC1:[0-9]+]]:[[SRC2:[0-9]+]]{{\]}} 29 ; GCN-DAG: v_rndne_f32_e32 v[[RND2:[0-9]+]], s[[SRC2]]
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D | sminmax.ll | 145 ; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]] 150 ; GFX9-DAG: v_sub_u32_e32 [[NEG2:v[0-9]+]], 0, [[SRC2:v[0-9]+]] 155 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC2]], [[NEG2]]
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/external/mesa3d/src/mesa/x86/ |
D | x86_xform3.S | 43 #define SRC2 REGOFF(8, ESI) macro 125 FLD_S( SRC2 ) /* F0 F7 F6 F5 F4 */ 127 FLD_S( SRC2 ) /* F1 F0 F7 F6 F5 F4 */ 129 FLD_S( SRC2 ) /* F2 F1 F0 F7 F6 F5 F4 */ 131 FLD_S( SRC2 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */ 214 FLD_S( SRC2 ) /* F0 F5 F4 */ 216 FLD_S( SRC2 ) /* F1 F0 F5 F4 */ 218 FLD_S( SRC2 ) /* F2 F1 F0 F5 F4 */ 228 MOV_L( SRC2, EBX ) 307 FLD_S( SRC2 ) /* F0 F6 F5 F4 */ [all …]
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D | x86_xform4.S | 43 #define SRC2 REGOFF(8, ESI) macro 125 FLD_S( SRC2 ) /* F0 F7 F6 F5 F4 */ 127 FLD_S( SRC2 ) /* F1 F0 F7 F6 F5 F4 */ 129 FLD_S( SRC2 ) /* F2 F1 F0 F7 F6 F5 F4 */ 131 FLD_S( SRC2 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */ 221 FLD_S( SRC2 ) /* F0 F5 F4 */ 223 FLD_S( SRC2 ) /* F1 F0 F5 F4 */ 225 FLD_S( SRC2 ) /* F6 F1 F0 F5 F4 */ 237 MOV_L( SRC2, EBX ) 317 FLD_S( SRC2 ) /* F0 F6 F5 F4 */ [all …]
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D | x86_cliptest.S | 38 #define SRC2 REGOFF(8, ESI) macro 169 MOV_L( SRC2, EBX ) 233 FLD_S( SRC2 ) /* F2 F1 F0 F3 */ 335 MOV_L( SRC2, EBX )
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D | x86_xform2.S | 43 #define SRC2 REGOFF(8, ESI) macro
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/external/llvm/test/CodeGen/SystemZ/ |
D | atomicrmw-minmax-02.ll | 162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769 163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]] 164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766 180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]] 181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 1 197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]], 198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65534 [all …]
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D | atomicrmw-minmax-01.ll | 162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 33024 163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]] 164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32256 180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]] 181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 256 197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]], 198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65024 [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
D | atomicrmw-minmax-01.ll | 162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 33024 163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]] 164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32256 180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]] 181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 256 197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]], 198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65024 [all …]
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D | atomicrmw-minmax-02.ll | 162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769 163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]] 164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766 180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]] 181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 1 197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]], 198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65534 [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/ |
D | copy_thumb.ll | 10 ; CHECK-LOLOMOV-NEXT: mov [[SRC1]], [[SRC2:r[01]]] 11 ; CHECK-LOLOMOV-NEXT: mov [[SRC2]], [[TMP]] 20 ; CHECK-NOLOLOMOV-NEXT: movs [[SRC1]], [[SRC2:r[01]]] 21 ; CHECK-NOLOLOMOV-NEXT: movs [[SRC2]], [[TMP]]
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/external/llvm/test/CodeGen/Thumb/ |
D | copy_thumb.ll | 10 ; CHECK-LOLOMOV-NEXT: mov [[SRC1]], [[SRC2:r[01]]] 11 ; CHECK-LOLOMOV-NEXT: mov [[SRC2]], [[TMP]] 23 ; CHECK-NOLOLOMOV: push {[[SRC2:r[01]]]} 27 ; CHECK-NOLOLOMOV-NEXT: pop {[[SRC2]]}
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/external/llvm/test/CodeGen/X86/ |
D | machine-cp.ll | 71 ; CHECK-NEXT: pcmpgtb [[SRC1]], [[SRC2:%xmm[0-9]+]] 72 ; CHECK-NEXT: pand %xmm{{[0-9]+}}, [[SRC2]] 73 ; CHECK-NEXT: movdqa [[SRC2]], [[CPY1:%xmm[0-9]+]]
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/external/llvm/test/CodeGen/AMDGPU/ |
D | sminmax.ll | 118 ; GCN-DAG: v_sub_i32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]] 123 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG2]], [[SRC2]]
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/external/mesa3d/src/mesa/state_tracker/tests/ |
D | test_glsl_to_tgsi_lifetime.cpp | 826 #define SRC2(X, S, Y, T) vector<pair<int, const char *>>({make_pair(X, S), make_pair(Y, T)}) macro 906 …MockCodelineWithSwizzle(TGSI_OPCODE_ADD, DST(out0, WRITEMASK_XYZW), SRC2(2, "yyzw", 1, "xyxy"), {}… in TEST_F()
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/external/u-boot/arch/arm/mach-tegra/tegra124/ |
D | clock.c | 144 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
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/external/u-boot/arch/arm/mach-tegra/tegra210/ |
D | clock.c | 146 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
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