Home
last modified time | relevance | path

Searched refs:SRC2 (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.exp.ll22 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
33 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
44 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
46 ; GCN: exp mrt0 off, off, [[SRC2]], off done{{$}}
55 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
66 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
77 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
79 ; GCN: exp mrt0 [[SRC0]], off, [[SRC2]], off done{{$}}
88 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
101 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
[all …]
Dcombine-ftrunc.ll27 ; GCN: s_load_dwordx2 s{{\[}}[[SRC1:[0-9]+]]:[[SRC2:[0-9]+]]{{\]}}
29 ; GCN-DAG: v_rndne_f32_e32 v[[RND2:[0-9]+]], s[[SRC2]]
Dsminmax.ll145 ; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]]
150 ; GFX9-DAG: v_sub_u32_e32 [[NEG2:v[0-9]+]], 0, [[SRC2:v[0-9]+]]
155 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC2]], [[NEG2]]
/external/mesa3d/src/mesa/x86/
Dx86_xform3.S43 #define SRC2 REGOFF(8, ESI) macro
125 FLD_S( SRC2 ) /* F0 F7 F6 F5 F4 */
127 FLD_S( SRC2 ) /* F1 F0 F7 F6 F5 F4 */
129 FLD_S( SRC2 ) /* F2 F1 F0 F7 F6 F5 F4 */
131 FLD_S( SRC2 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
214 FLD_S( SRC2 ) /* F0 F5 F4 */
216 FLD_S( SRC2 ) /* F1 F0 F5 F4 */
218 FLD_S( SRC2 ) /* F2 F1 F0 F5 F4 */
228 MOV_L( SRC2, EBX )
307 FLD_S( SRC2 ) /* F0 F6 F5 F4 */
[all …]
Dx86_xform4.S43 #define SRC2 REGOFF(8, ESI) macro
125 FLD_S( SRC2 ) /* F0 F7 F6 F5 F4 */
127 FLD_S( SRC2 ) /* F1 F0 F7 F6 F5 F4 */
129 FLD_S( SRC2 ) /* F2 F1 F0 F7 F6 F5 F4 */
131 FLD_S( SRC2 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
221 FLD_S( SRC2 ) /* F0 F5 F4 */
223 FLD_S( SRC2 ) /* F1 F0 F5 F4 */
225 FLD_S( SRC2 ) /* F6 F1 F0 F5 F4 */
237 MOV_L( SRC2, EBX )
317 FLD_S( SRC2 ) /* F0 F6 F5 F4 */
[all …]
Dx86_cliptest.S38 #define SRC2 REGOFF(8, ESI) macro
169 MOV_L( SRC2, EBX )
233 FLD_S( SRC2 ) /* F2 F1 F0 F3 */
335 MOV_L( SRC2, EBX )
Dx86_xform2.S43 #define SRC2 REGOFF(8, ESI) macro
/external/llvm/test/CodeGen/SystemZ/
Datomicrmw-minmax-02.ll162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 1
197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]],
198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
[all …]
Datomicrmw-minmax-01.ll162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 256
197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]],
198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Datomicrmw-minmax-01.ll162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 256
197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]],
198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
[all …]
Datomicrmw-minmax-02.ll162 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
163 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
164 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
179 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
180 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
181 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
196 ; CHECK: llilh [[SRC2:%r[0-9]+]], 1
197 ; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]],
198 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
213 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/
Dcopy_thumb.ll10 ; CHECK-LOLOMOV-NEXT: mov [[SRC1]], [[SRC2:r[01]]]
11 ; CHECK-LOLOMOV-NEXT: mov [[SRC2]], [[TMP]]
20 ; CHECK-NOLOLOMOV-NEXT: movs [[SRC1]], [[SRC2:r[01]]]
21 ; CHECK-NOLOLOMOV-NEXT: movs [[SRC2]], [[TMP]]
/external/llvm/test/CodeGen/Thumb/
Dcopy_thumb.ll10 ; CHECK-LOLOMOV-NEXT: mov [[SRC1]], [[SRC2:r[01]]]
11 ; CHECK-LOLOMOV-NEXT: mov [[SRC2]], [[TMP]]
23 ; CHECK-NOLOLOMOV: push {[[SRC2:r[01]]]}
27 ; CHECK-NOLOLOMOV-NEXT: pop {[[SRC2]]}
/external/llvm/test/CodeGen/X86/
Dmachine-cp.ll71 ; CHECK-NEXT: pcmpgtb [[SRC1]], [[SRC2:%xmm[0-9]+]]
72 ; CHECK-NEXT: pand %xmm{{[0-9]+}}, [[SRC2]]
73 ; CHECK-NEXT: movdqa [[SRC2]], [[CPY1:%xmm[0-9]+]]
/external/llvm/test/CodeGen/AMDGPU/
Dsminmax.ll118 ; GCN-DAG: v_sub_i32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]]
123 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG2]], [[SRC2]]
/external/mesa3d/src/mesa/state_tracker/tests/
Dtest_glsl_to_tgsi_lifetime.cpp826 #define SRC2(X, S, Y, T) vector<pair<int, const char *>>({make_pair(X, S), make_pair(Y, T)}) macro
906 …MockCodelineWithSwizzle(TGSI_OPCODE_ADD, DST(out0, WRITEMASK_XYZW), SRC2(2, "yyzw", 1, "xyxy"), {}… in TEST_F()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c144 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c146 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),