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Searched refs:SRC_DDR1_ENABLE_MASK (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx8m/
Dclock.c546 writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr); in dram_pll_init()
547 writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr); in dram_pll_init()
/external/u-boot/arch/arm/include/asm/arch-mx8m/
Dimx-regs.h143 #define SRC_DDR1_ENABLE_MASK 0x8F000000UL macro